Oki Electric Industry Co., Ltd.

Lapis Semiconductor Co., Ltd.

Sony Corporation

Oki Semiconductor Co., Ltd.

Sumco Corporation

Mitsui Kensetsu Kabushiki Kaisha

Kazutoshi Inoue

Mitsuya Ohie

Atsushi Yusa

Naoyuki Wada

Tomofumi Arakawa

Hiroaki Kodama

Toshihide Nagatome

Yoshikatsu Matsuo

Shigeo Takamiya

Katsutoshi Yoshimura

Kenzo Tsutaya

There is provided an oscillation circuit including: a main oscillation circuit that outputs a specific main clock to an internal circuit; a sub oscillation circuit that outputs a sub clock having a different frequency to the frequency of the main oscillation circuit; a first abnormality detection section that detects an abnormality according to a number of main clock cycles output from the main oscillation circuit within a predetermined period corresponding to sub clock outputs from the sub oscillation circuit; and a second abnormality detection section that detects an abnormality according to a frequency divided clock of the main clock output from the main oscillation circuit that has been frequency-divided and the sub clock output from the sub oscillation circuit.

Oscillation circuit, integrated circuit, and abnormality detection method

An electrical device includes a plurality of apparatus connected with a daisy chain connection through a communication line so that the apparatus communicate with each other through the communication line; and a control unit connected to one of the apparatus at an end stage thereof so that the control unit is configured to communicate with the one of the apparatus. The apparatus includes an address setting unit for setting a specific number to an address of the apparatus according to an address setting command when the apparatus receives address setting data including an address addition instruction as the address setting command for adding the specific number to the address of the apparatus. The apparatus further includes an address setting data transmission control unit for outputting the address setting data to a later stage apparatus when the address setting unit sets the specific value to the address of the apparatus.

Electrical device and method of setting address

There is provided a semiconductor circuit including: a selection circuit, to which are connected batteries in series, and which selects any one of the batteries; a difference detecting circuit, to which voltage of a high potential side of the selected battery inputted, and to which voltage of a low potential side of the selected battery is inputted, and which outputs a difference between the voltage at the high-potential side and the voltage at the low-potential side; and a voltage applying unit that applies diagnostic voltage to a wire that is for inputting the high potential voltage to the difference detecting circuit when diagnosing an abnormality of a wire associated with the selected battery if the selected battery is a battery of a highest position in the series or a battery of a lowest position in the series.

Semiconductor circuit, semiconductor device, method of diagnosing abnormality of wire, and computer readable storage medium

In a signal processor including storage sections, a start address for starting output of data from an external memory, is input from an external controller to the start address input section. The signal output section outputs a start signal based on a download start instruction from the external controller, and outputs an end signal when download is completed. The output instruction section outputs, based on the start signal, to the external memory a data output instruction of download data for a designated storage section, starting from the start address, and stops output of the data output instruction based on the end signal. The write instruction section outputs a write instruction to the storage sections that allows data writing only to the designated storage section, and the download data is written to the designated storage section when the start signal is input to the output instruction section.

Signal processor and signal processing system

A process for producing a silicon wafer by conveying a (100) face silicon wafer into and from a treating furnace of a single wafer heat-treating apparatus or a vapor phase growth apparatus with a conveying blade having a mounting face capable of mounting only a specified region of the wafer inclusive of a center position of its rear face for subjecting the wafer to a heat treatment or a vapor phase growth, in which &#x3c;010&#x3e; or &#x3c;001&#x3e; orientation is shifted by a predetermined angle with respect to a transverse direction of the mounting face of the conveying blade.

Method for unloading thermally treated non-planar silicon wafers with a conveying blade

A semiconductor device able to improve data retaining characteristics and decrease power consumption, further able to realize more unrestricted system without increasing excessive circuits, and having the following: an ALPG receiving a start signal and a mode selection signal to generate commands and addresses with respect to a DRAM circuit with the predetermined patterns in accordance with modes, and outputting an ending signal when ending a pattern generating processing in each of modes; an ECC circuit receiving a start signal and a mode selection signal indicating a parity generation mode to generate a parity based on data read from the DRAM circuit, receiving the start signal and a mode selection signal indicating an error correction mode to perform an error correction with respect to data read from the DRAM circuit based on the parity generated in the parity generation mode and outputting data after correcting; and an interface circuit.

Semiconductor device to improve data retention characteristics of DRAM

A semiconductor integrated circuit for performing processing relating to a test of a plurality of memory units provided therein while suppressing an increase of a circuit area is provided, wherein testing input data generated in a testing circuit is shifted successively on registers of a first data shift circuit formed by scan flip-flops and transferred to each memory unit when carrying out a test on a plurality of memory units, and testing output data in accordance with the testing input data is shifted successively on registers of a second data shift circuit formed by using scan flip-flops and retrieved by the testing circuit.

Semiconductor integrated circuit

A microcontroller of the present invention includes: input/output ports; peripheral functional blocks, associated with the input/output ports, for performing predetermined functions; a clock signal generating circuit; a function selection decoder circuit for decoding a mode signal input from function selection pins and outputting a function selection signal; a clock signal controlling section for controlling supply/stop of a clock signal to each of the functional blocks in response to the function selection signal; and a port controlling block for setting functions of the input/output ports in response to the function selection signal.

Microcontroller with multiple function blocks and clock signal control

A MCP semiconductor device includes at least first and second chips, each of which has internal pads and an internal circuit, encapsulated by a sealing material together. The device further includes a test circuit. The test circuit connects each of the internal pads to one of the internal circuits under a normal operation mode of the device, and disconnect between them under a test mode.

Test circuit and multi-chip package type semiconductor device having the test circuit

In a clock control circuit there are provided a counter for dividing a reference clock signal so as to generate a plurality of divided clock signals and selectors for selectively outputting one of the plurality of divided clock signals and the reference clock signal as an operation clock signal relative to a CPU or as an operation clock signal relative to a peripheral circuit.

Clock control circuit

An integrated circuit in which Schmitt input circuits can be tested in a short time and a highly accurate test result can be obtained. The integrated circuit includes switches each passing outputs of Schmitt inverters with inputs connected to input-output ports to the inputs of tristate circuits with outputs connected to adjacent input-output ports. The outputs of the Schmitt inverters may be blocked by the switches from being passed to internal logical circuits. A switch passes the output of the Schmitt inverter to the adjacent tristate circuit during the test of the Schmitt inverter. Alternately, each half of the Schmitt inverters can be tested as predetermined control signals selectively control each switch and each tristate circuit.

Growing community of inventors

Tokyo, Japan

Kazutoshi Inoue