Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Socionext Inc.

Kazutoshi Funahashi

Manabu Kuroda

Atsuhisa Kageyama

Yoshihiro Koga

Satoshi Ikawa

Noboru Asai

Shotaro Itakura

Masaru Nagayasu

An image correction device generates a corrected image for a viewer with low vision, by adding excessive emphasis which reduces image quality as perceived by a viewer having normal eyesight, to at least one of luminance gradation, luminance contour, and color tone of a pre-correction image. The image correction device includes: a controller which specifies, in a low vision mode which is an image correction mode for the viewer with low vision, a parameter that represents an amount of correction greater than an upper limit of an amount of correction which does not reduce the image quality as perceived by the viewer having normal eyesight when the pre-correction image is corrected; and an image processor which generates the corrected image by correcting the at least one of the luminance gradation, the luminance contour, and the color tone of the pre-correction image with the amount of correction represented by the parameter.

Image correction device and video content reproduction device

The data sharing apparatus in the present invention includes a first processor and a second processor, each of a different endianness, that are both connected to the memory via the data bus, in a byte order based on the endianness of the first processor. It also includes an address conversion unit which converts at least one lower bit of an address to indicate a reversed position of data in the data bus, and outputs the converted address to the memory, in the case where the second processor performs a memory access on the shared memory for data with a smaller width than the data bus.

Data sharing apparatus and processor for sharing data between processors of different endianness

A semiconductor device has a processor, a first memory unit accessed by the processor, a plurality of page memory units obtained by partitioning a second memory unit which is accessible by the processor at a speed higher than the speed at which the first memory unit is accessible such that each of the page memory units has a storage capacity larger than the memory capacity of a line composing a cache memory, a tag adding, to each of the page memory units, tag information indicative of an address value in the first memory unit and priority information indicative of a replacement priority, a tag comparator for comparing, upon receipt of an access request from the processor, the address value in the first memory unit with the tag information held by the tag, and a replacement control unit for replacing the respective contents of the page memory units.

Memory replacement mechanism in semiconductor device

The image processor of the present invention includes: an extracting means, an entropy decoding means, a combining means, and an inverse orthogonal transformation means. Coded data at respective stages in a certain block are extracted by the extracting means, and entropy-decoded by the entropy-decoding means, to obtain coefficient data at the respective stages in the block. The coefficient data at the respective stages are combined by the combining means to obtain coefficient data for the block. The coefficient data is subjected to inverse orthogonal transformation by the inverse orthogonal transformation means, to attain original image data for the block. The above series of processing are performed for all blocks, to attain an original image on the entire screen. The memory capacity required for combining the coefficient data at the respective stages may only be large enough to store coefficient data for one block.

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Osaka, Japan

Kazutoshi Funahashi