Hitachi, Ltd.

Kazutoshi Ashikawa

Terumi Takashi

Isao Yoshida

Shoichi Miyazawa

Eisaku Saiki

Takeaki Okabe

Shintaro Suzumura

Tsuguyoshi Hirooka

Mitsuo Ito

Seiichi Mita

Tetsuo Iijima

Masashi Mori

Yoshio Sakai

Toshiaki Masuhara

Osamu Minato

Minoru Nagata

Kazunori Iwabuchi

Akihiko Hirano

Hideaki Kato

Takushi Nishiya

Kazuhisa Shiraishi

Ryushi Shimokawa

Mineo Katsueda

Yoshiteru Ishida

Hideyuki Yamakawa

Shigeo Ohtaka

A magnetic recording and reproducing apparatus includes a R/W signal processor having a write data generator arranged to be of an interleave system and transmitting/receiving data to/from the R/W amplifier via a plurality of signal lines. In addition, the R/W amplifier has a compound circuit provided for the write data of the interleave system from the R/W signal processor and is formed as an integrated circuit, moreover, a &frac12; prescaler is provided at the output of the write data generator, making transmitting and receiving write data in NRZI CODE.

Magnetic recording and reproducing apparatus and semiconductor integrated circuit for use in the same comprising a read/write signal processor having an interleave write data generator

A magnetic recording and reproducing apparatus includes a read/write signal processor having a write data generator arranged to be of an interleave system and transmitting/receiving data to/from the read/write amplifier via a plurality of signal lines. In addition, the read/write amplifier has a compound circuit provided for the write data of the interleave system from the read/write signal processor and is formed as an integrated circuit, moreover, a 1/2 prescaler is provided at the output of the write data generator, transmitting and receiving write data in Non-Return-To-Zero-Interleave CODE.

Magnetic recording and reproducing apparatus and a read/write amplifier having a signal transmission system with high speed of data write signal

A magnetic recording and reproducing apparatus such as a disk drive has a phase locked loop circuit which is less susceptible to an effect of noise of a power supply and ground and reduces a clock jitter. The magnetic recording and reproducing apparatus is compatible to a constant density recording system without increasing a circuit scale and a power consumption and with a small number of IC pins. The phase locked loop circuit of the magnetic recording and reproducing apparatus is provided with two D/A converter circuits to drive a loop filter. It is also provided with a circuit for distributing a reference potential of a voltage controlled oscillator (VCO) and a center frequency of the VCO, a gain of the VCO and a current gain of the D/A converter circuit are changed in linked relation. A reference voltage source is provided such that a center point or one end of the loop filter is connected to the reference voltage eliminating the ground connection.

Data recording and reproducing apparatus and phase locked loop circuit

A playback signal processing circuit for reducing decode errors and enabling high-density digital magnetic recording and a digital magnetic recording reproducing unit using the playback signal processing circuit are provided. An estimated waveform generation circuit uses the decoding result of a PRML channel to generate an ideal playback signal waveform. A subtractor provides a waveform representing a difference between the waveform and an actual playback signal. There is a high probability that error bits will occur at an interval of two or four bits because of the nature of GCR code and maximum-likelihood decoding; in the error state of each bit, one bit is incremented by one with respect to the correct bit value and the other signal bit is decremented by one. From this fact, an error detection circuit discriminates an error difference waveform pattern and an error discrimination circuit detects an error bit interval, whereby an error correction circuit carries out error bit correction.

Digital signal processor, error detection method, and recording medium

A clock timing extraction circuit for use in an information recording/reproducing apparatus has a phase comparator for comparing the reproduced signal with a selected clock signal to generate a phase error signal, a clock signal generation circuit for adjusting frequency to cause the error signal to approach zero according to the phase error signal and outputting a plurality of clock signals having mutually different phase differences, a selection circuit for outputting one of the plurality of clock signals on the basis of a selection signal, a phase difference judgement circuit for determining one of the plurality of clock signals having a minimum phase error (Vdet) and generating a selection signal for selection of the clock signal having the minimum phase difference, and a freeze circuit for blocking an output of the phase comparator until the clock signal having the minimum phase error is selected. The information recording/reproducing apparatus has an AGC circuit for limiting an amplitude of a reproduced signal received from a recording medium, the aforementioned clock timing extraction circuit, and a decoder circuit. The clock timing extraction circuit extracts a clock signal from an output signal of the AGC circuit and the decoder decodes the output signal of the AGC circuit on the basis of the extracted clock signal.

Information recording/reproducing apparatus having a clock timing

An insulated gate semiconductor device contains a protective element for protecting the gate electrode of an insulated gate field effect transistor. The protective element is formed of the same semiconductor layer as that of the gate electrode of the insulated gate field effect transistor and is formed integrally with the gate electrode on an insulating film formed on the surface of a semiconductor substrate.

Insulated gate semiconductor device with back-to-back diodes

A method for fabrication a vertical MOSFET which contains a protective element for protecting the gate electrode of an insulated gate field effect transistor. The protective element is formed of the same semiconductor layer as that of the gate electrode of the insulated gate field effect transistor and is formed integrally with the gate electrode on an insulating film formed on the surface of a semiconductor substrate.

Method for fabricating vertical MOSFETs

A semiconductor integrated circuit device is provided to include a vertical type MOSFET and a gate protection element for the MOSFET. The vertical type MOSFET is made up of a silicon layer of n-type conductivity formed on an n.sup.+ -type silicon substrate, a base region of p-type conductivity formed in the surface of the silicon layer of n-type conductivity, an n.sup.+ -type source region provided in the base region, and a gate electrode formed on a portion of the base region through a gate insulating film. The silicon substrate serves as the drain. The gate protection element is formed of a polycrystalline silicon layer which is provided on the base region through an insulating film and includes at least one pn junction. By virtue of forming the gate protection element over the base region rather than directly over the substrate, a more stable operation is achieved.

DMOS With gate protection diode formed over base region

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Maebashi, Japan

Kazutoshi Ashikawa