Renesas Electronics Corporation

Fujitsu Corporation

Nec Electronics Corporation

Kazutaka Taniguchi

Yasuhiro Tonda

Hidetoshi Ozoe

Shinya Tashiro

Yasuhiro Suzuki

Atsushi Kaneko

Hiroki Koga

Seiya Shindo

Eiji Mizunuma

Yuichiroh Takoh

Hisaya Fujii

A non-transitory computer-readable storage medium storing a program that causes a computer to execute a process, the process including executing one of a plurality of programs, acquiring a status of variation in an internal state of a memory occurred in response to the executing, determining whether a specified status pattern is stored in a storage device that stores a plurality of status patterns of variation in an internal state of the memory, the specified status pattern satisfying a predetermined criterion regarding a similarity with the acquired status, when the specified status pattern is stored in the storage device, generating a test scenario that is a combination of programs including the executed program, and when the specified status pattern is not stored in the storage device, suppressing the generating the test scenario.

Non-transitory computer-readable storage medium, generation method, and information processing apparatus

To improve reading accuracy of a sense amplifier circuit and a semiconductor memory device. A sense amplifier circuit includes an N type FET which is a sensing transistor connected between a power supply and a ground via a data line that extends to a memory cell, a resistance element that is connected between a gate of the sensing transistor and the power supply, and a capacitance element that is connected between the gate of the sensing transistor and the ground.

Sense amplifier circuit and semiconductor memory device

A semiconductor device includes a power-supply circuit which produces a first voltage potential, a first terminal, a second terminal which receives a mode signal, an inverter which receives the mode signal and outputs an inverted mode signal, and a first transfer circuit which includes a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor coupled between the power-supply circuit and a first node, the second transistor coupled between the power-supply circuit and the first node in parallel with the first transistor, a control gate of the first transistor supplied with the inverted mode signal and a control gate of the second transistor supplied with the mode signal.

Semiconductor device having CMOS transfer circuit and clamp element

A semiconductor device includes an internal power-supply circuit which produces an internal potential, an external terminal which outputs the internal potential and inputs and outputs a signal with an outside, and a test mode signal terminal which transfers a test mode signal. The semiconductor device further includes a first CMOS transfer circuit and a second CMOS transfer circuit which are provided between the internal power-supply circuit and the external terminal, and which are controlled by the test mode signal, a clamp element which is connected between the first and second CMOS transfer circuits and suppresses a potential variation, and a delay element provided between the clamp element and the first CMOS transfer circuit.

A self-refresh control circuit includes a first constant current generating circuit that generates a constant current to change depending on the temperature, a second constant current generating circuit to generate a constant current not depending on the temperature, a current-cycle converting circuit selectively connected to the first constant current generating circuit and the second constant current generating circuit and converting the constant currents inputted from the first constant current generating circuit and the second constant current generating circuit into a test refresh cycle used for setting the refresh cycle.

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Yokohama, Japan

Kazutaka Taniguchi