Kabushiki Kaisha Toshiba

Thine Electronics, Inc.

Kazutaka Nogami

Takayasu Sakurai

Fumitoshi Hatori

Yukihiro Fujimoto

Kazuhiro Sawada

Tsuguo Kobayashi

Makoto Takahashi

Tsukasa Shirotori

Makoto Ichida

Shigeru Tanaka

Masami Masuda

Syuso Fujii

Mitsuo Isobe

Masakazu Kakumu

Hisashi Ueno

Shinji Kitabayashi

Masanori Uchida

Sumako Shiraishi

Yuki Satoh

Tatsuya Higashi

In a semiconductor integrated circuit including a phase comparator circuit for a PLL or DLL, overall lock precision of the PLL or DLL is improved by eliminating a dead zone of the phase comparator circuit and preventing output current offset of a charge pump circuit. The semiconductor integrated circuit includes a first circuit for activating a first phase difference signal corresponding to a phase difference between a first clock signal and a second clock signal when a phase of the first clock signal is delayed by more than a predetermined value in comparison with a phase of the second clock signal and activating a second phase difference signal corresponding to the phase difference when the phase of the first clock signal is advanced by more than a predetermined value in comparison with the phase of the second clock signal, a second circuit for activating a first pulse signal when an edge of the first clock signal is delayed in comparison with an edge of the second clock signal and activating a second pulse signal when the edge of the first clock signal is advanced in comparison with the edge of the second clock signal, a third circuit for combining the first phase difference signal and the first pulse signal, and a fourth circuit for combining the second phase difference signal and the second pulse signal.

Semiconductor integrated circuit

An adder comprises: a comparator circuit for comparing values of n input signals, each of which comprises 1-bit data, with first to n-th predetermined values which are different from each other; a non-volatile memory having first to n&plus;1-th word lines, m (2 &gE;n&plus;1) bit lines which are provided so as to intersect the word lines, and memory cells, each of which is provided at an intersection of each of the word lines and each of the bit lines and each of which has stored 1-bit data; and a selector circuit for selecting one of the n&plus;1 word lines on the basis of n comparison results of the comparator circuit to activate the selected word line. Thus, a plurality of bits are added at high speed.

Adder

A data transmission circuit has a push-pull circuit including first and second MOS transistors, sequentially connected in series between a first power source potential node and a second potential node, to which a first data signal and a second data signal defined as an inverted signal of the first data signal are respectively supplied, an output capacitance connected between the second power source potential node and a connecting node between the MOS transistor and the second MOS transistor which serves as an output node of the push-pull circuit, a transfer gate connected to the output node of the push-pull circuit, a first inverter connected to the output node of the transfer gate, and a second inverter connected to the first inverter to form a feedback loop, whereby the data are transmitted by a low quantity of consumed electric power.

Data transmission circuit

A semiconductor integrated circuit apparatus comprises a semiconductor substrate, a first well region formed in the upper surface of the semiconductor substrate, a first circuit formed in the first well region, first bias voltage supply functions for supplying a bias voltage to the first well region, a second well region formed in the upper surface of the semiconductor substrate such that it does not contact the first well region, a second circuit formed in the second well region, and second bias voltage supply functions for supplying a bias voltage to the second well region.

Semiconductor integrated circuit apparatus having a plurality of well

The address translation device includes a virtual page number register for storing a last-accessed virtual page number, a physical page number register for storing a physical page number corresponding to the virtual page number stored in the virtual page number and a TLB (translation lookaside buffer) circuit for storing a plurality of relationships between the physical page numbers and the virtual page numbers. First, a comparator compares a new virtual page number with an output of the virtual page number register. If the new virtual page number matches the output of the virtual page number register, the output of the physical page number register is output through a multiplexer as a physical page number. If the new and stored page numbers do not match, on the other hand, a mismatch signal output by the comparator activates the TLB circuit so that the output of the TLB circuit is outputted through a multiplexer as the physical page number. Different configurations of the TLB circuit are used in such a way that the processing speed can be secured without reducing the hit ratio of the address translation. Further, the access to the TLB circuit is minimized to reduce the power consumption.

Address translation device storage last address translation in register

A signal processor includes an instruction buffer for sequentially storing information on instructions output from an instruction cache, and a first register that detects that an instruction enters in an instruction loop. When the instruction loop is formed, a control circuit controls the instruction buffer to supply the instruction in the instruction loop from its storage while placing the instruction cache in an inactive state.

Signal processor and method of operating a signal processor

A single-port memory or a multi-port memory with a higher density than conventional memory devices is realized, while using the same design rule, by decreasing the number of bit lines per column or port to decrease the space for wiring and the size of the entire memory. A memory circuit includes a memory cell array arranging a plurality of memory cells in a matrix, each memory cell having at least one read port; word lines each connected to memory cells aligned in a row among the memory cells of the memory cell array, and bit lines each connected to memory cells aligned in n rows (n.gtoreq.2) among the memory cells of the memory cell array. Current drivability of access transistors of memory cells sharing n bit lines are set to satisfy the relation of 1:2: . . . :2.sup.n-1. This results in decreasing the number of bit lines and the area of the memory.

Memory circuit

In the output buffer circuit, when an enable signal is inputted to deactivate the main buffer circuit (MB1) and further when a voltage higher than the first supply voltage V.sub.DD is applied to the output terminal (I/O), since the fifth P-type transistor (QP2) is turned on, the voltage at the output terminal is applied to the gate of the third P-type transistor (QP1), so that this transistor (QP1) is perfectly turned off. Therefore, it is possible to prevent unnecessary current from flowing from the output terminal (I/O) to the first supply voltage (V.sub.DD) terminal through the third P-type transistor (QP1). Further, since the sixth P-type transistor (QP4) is turned on, the voltage at the output terminal is applied to the gate of the second P-type transistor (QP6) through the sixth P-type transistor (QP4), so that this transistor (QP6) can be perfectly turned off. Therefore, it is possible to prevent unnecessary current from flowing to the first supply voltage (V.sub.DD) terminal through the first and second P-type transistors (QP5 and QP6). Further, since a voltage higher than the first supply voltage will not be applied to the gate oxide film of the second to sixth P-type transistors all formed on the same N-type substrate, it is possible to prevent the manufacturing process from being complicated.

Output buffer circuit

A method for processing data by utilizing hierarchial cache memories in a system where a lower cache is connected between a processor and a higher cache memory and the higher cache memory is in turn connected to a main memory or connected through a serial arrangement of higher cache memories to the main memory. When a cache miss occurs in the lower cache and the lower cache is full of 'dirty data', the data is not written to the main memory but instead to the higher cache. Dirty data is written into the main memory when at least all of the cache memories are filled with dirty data and a cache miss occurs.

Method for processing data by utilizing hierarchical cache memories and

A semiconductor device comprising a main circuit having a p-channel MOSFET formed on the surface off the substrate and an n-channel MOSFET formed on the p-type well region which is formed on the n-type Si substrate chip), an input/output (I/O) circuit formed on the substrate, and a substrate bias generating circuit formed on the substrate, characterized by controlling the substrate bias generating circuit via the I/O circuit, and varying a bias supplied to the substrate and the p-type well region, in accordance with the operation mode of the main circuit.

Semiconductor device

A clock signal generation circuit performs a stable operation with respect to both a high frequency input clock signal and a sufficient low frequency testing clock signal. The circuit includes a phase comparator for generating a phase difference output corresponding to a phase difference between an internal clock signal and a reference clock signal externally supplied; a frequency distinction circuit for generating a frequency change-over signal when a frequency of the reference clock signal is lower than a preset reference signal; a loop filter for generating an output voltage corresponding to the phase difference output and for changing over a filter constant to that for a low frequency corresponding to the frequency change-over signal; and a voltage control oscillator for setting a frequency of the internal clock signal to a frequency corresponding to the output voltage of the loop filter and for decreasing a change amount of an oscillating frequency with respect to an input signal corresponding to the frequency change-over signal.

Clock signal generation circuit capable of operating at high speed with

A field programmable gate array comprises: a first wire group (8) composed of a plurality of first wires; a second wire group (7) composed of a plurality of second wires; switching sections (9) provided at least one intersection between the first and second wires of the first and second wire groups (8, 7), for determining connection and disconnection between both when programmed; and a basis cell (6B) having a first transmission gate (4) turned on in response to a high gate voltage and a second transmission gate (5) turned on in response to a low gate voltage, gates of the first and second transmission gates (4, 5) being connected to each other as a common gate or being connectable to each other as a common gate by the switching sections when programmed, input and output terminals and the common gates of the first and second transmission gates (4, 5) being connected to any of the first wires of the first wire group (8), respectively. Wiring of different lengths is provided for connecting circuit elements within the field programmable gate array, with wires of a first length being more numerous than wires of a second, longer length. The quantity of wires of different lengths varies in accordance with the -2.5 power of the length of the wires.

Field programmable gate array having transmission gates and

A field programmable gate array comprises: a first wiring group composed of a plurality of first wirings (C1, C2, C3, . . . ); a second wiring group composed of a plurality of second wirings (R1, R2, R3, . . . ); a plurality of programmable elements (A11, A12, A13, . . . ) arranged into an array pattern at at least one of plural intersections between the first wirings and the second wirings, each of the programmable element being connected to each of the first wirings (C1, C2, C3, . . . ) at one end thereof and to each of the second wirings (R1, R2, R3, . . . ) at the other end thereof and being programmed by a programming voltage applied between the first wiring and second wiring to switch connection between the first and second wirings to disconnection between the two wirings or vice versa; and voltage supplying sections (CD1, RD1) for applying a programming voltage between the first and second wirings (C1, C2, C3, . . . ; R1, R2, R3, . . . ) between which the programmable element to be programmed is connected and an intermediate voltage between the first and second wirings between which the programmable element not to be programmed is connected, the intermediate voltage being lower than the programming voltage to such an extent as not to affect state of the programmable elements (A11, A12, A13, . . . ).

Field programmable gate array

A data output circuit includes a P-channel transistor having a source connected to a supply voltage terminal V.sub.DD and a gate coupled to receive a drive signal from an internal circuit, and an N-channel transistor having its drain connected to the drain of the P-channel transistor and its source connected to an output terminal D.sub.out. The threshold voltage of the N-channel transistor is fixed to be lower than the thresholds of other N-channel transistors formed on the same substrate. A high level signal is output from the output terminal D.sub.out when a voltage output by the supply voltage terminal V.sub.DD is supplied to the output terminal D.sub.out through the P-channel transistor and the N-channel transistor. In this configuration; the output terminal charges quickly using the high driving capability of the N-channel transistor. Since the N-channel transistor is interposed along the current path from the output terminal to the supply voltage terminal, current does not flow from the output terminal to the supply voltage terminal when a voltage higher than the supply voltage is applied to the output terminal.

Data output circuit for semiconductor integrated circuit device which

A semiconductor memory device capable of reducing power consumption has a memory cell array, a plurality of address lines, a pair of data lines, an address transition detector circuit for outputting an address transition signal in response to a change in a signal on the address line, a sense amplifier, a sense amplifier control circuit for activating the sense amplifier in response to the address transition signal and deactivating the sense amplifier in response to the sense amplifier output signal, and a word line control circuit which deactivates the word lines within the memory cell array in response to the sense amplifier control circuit.

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Tokyo, Japan

Kazutaka Nogami