Nec Corporation

Elpida Memory, Inc.

Ps4 Luxco S.a.r.l.

Other

Longitude Semiconductor S.a.r.l.

Kazutaka Manabe

Satoru Yamada

Kensuke Okonogi

Kiyonori Ohyu

Takuo Ohashi

Eiji Kitamura

A device includes a semiconductor region surrounded with the isolation region and includes a first active region, a channel region and a second active region arranged in that order in a first direction. A first side portion of the first active region and a second side portion of the second active region faces each other across a top surface of the channel region in the first direction. A gate electrode covers the top surface and the first and second side portions and extends in a second direction that intersects the first direction. A first diffusion layer is formed in the first active region. A second diffusion layer is formed in the second active region. An embedded contact plug is formed in the first active region and extends downwardly from the upper surface of the semiconductor region and contacts with the first diffusion layer.

Memory transistors with buried gate electrodes

A semiconductor device includes the following elements. A semiconductor substrate includes an isolation region. The semiconductor substrate has a groove in the isolation region. A pad electrode is disposed in the groove. A pad contact plug is disposed in the groove. The pad contact plug is disposed on the pad electrode. A gate contact plug is disposed on the pad contact plug. The gate contact plug is electrically coupled through the pad contact plug to the pad electrode. An insulating side wall is disposed in the groove. The insulating side wall covers side surfaces of the pad contact plug and a lower portion of the gate contact plug, and the insulating side wall covers a part of an upper surface of the pad electrode.

Semiconductor device, method of forming semiconductor device, and data processing system

A semiconductor device includes: a semiconductor substrate; a pair of first diffusion layer regions provided near a top face of the semiconductor substrate; a channel region provided between the first diffusion layer regions of the semiconductor substrate; a gate insulation film provided on the channel region and on the semiconductor substrate such as to overlap with at least part of the first diffusion layer regions; a gate electrode provided on the insulation film; a pair of silicon selective growth layers provided on the semiconductor substrate at both sides of the gate electrode, each of the pair of silicon selective growth layers overlapping with at least part of the first diffusion layer regions, and being provided at a distance from the gate electrode; second diffusion layer regions provided in each of the silicon selective growth layers, peak positions of impurity concentration of the second diffusion layer regions being shallower than bottoms of the silicon selective growth layers; and third diffusion layer regions provided near side faces of the silicon selective growth layers, and electrically connecting the first diffusion layer regions to the second diffusion layer regions.

Semiconductor device and manufacturing method thereof

A method of manufacturing a semiconductor device forms an Ndiffusion layer to be a source/drain region of a grooved transistor simultaneously with an Ndiffusion layer of a channel region directly under a gate electrode of an antifuse element. The formation of the Ndiffusion layer directly under the gate electrode of the antifuse element stabilizes electrical connection between the gate electrode and the source/drain diffusion region even during writing with a low write voltage.

Method of manufacturing semiconductor device

A method for manufacturing a DRAM device on a silicon substrate includes: forming cell transistors in a memory cell area and other transistors in a peripheral circuit area; forming polysilicon plugs connected to diffused regions of the cell transistors and metallic plugs connected to diffused regions of the other transistors; heat treating at a temperature of 980 to 1,020 degrees C.; heat treating at a temperature of 700 to 850 degrees C.; implanting fluorine or boron fluoride into the diffused regions of the other transistors; and heat treating at a temperature of 500 to 850 degrees C.

Method for manufacturing a semiconductor device having polysilicon plugs

A method of manufacturing a semiconductor device of the present invention consists of forming a trench in a trench-type cell transistor region; forming a gate insulating film and a gate material layer on a semiconductor substrate; forming a photoresist layer on the semiconductor substrate so as to expose extension region formation portions of the trench-type cell transistor region and a high breakdown voltage transistor region; forming extension regions in each region by performing ion implantation in the semiconductor substrate surface of the trench-type cell transistor region and the high breakdown voltage transistor region and then patterning gates, and forming extension regions of an ordinary breakdown voltage transistor by covering the trench-type cell transistor region and the high breakdown voltage transistor region with a photoresist layer and implanting ions in the ordinary breakdown voltage transistor region.

A semiconductor device including an IGFET (insulated gate field effect transistor) () is disclosed. IGFET () may include a source/drain area () having an impurity concentration distribution that may be formed shallower at a higher concentration than the impurity concentration distribution in another source/drain area (). A gate oxide film may include a first gate oxide film () adjacent to source/drain area () and a second gate oxide film () adjacent to source drain area (). Second gate oxide film () may be thinner than first gate oxide film (). An impurity concentration distribution of a second channel impurity area () under second gate oxide film () may be at a higher concentration than an impurity concentration distribution of a first channel impurity area () under first gate oxide film (). In this way, an electric field at a PN junction of source/drain area () may be reduced.

Semiconductor device and its manufacturing method

In a semiconductor device ( ), plural diffusion layer areas ( ) are formed so that the impurity concentration of the diffusion layer area ( ) is set to be higher than that of the diffusion layer area ( ), and a first contact wire ( ) connected to the diffusion layer area ( ) having the higher impurity concentration is set to be larger in sectional area than a second contact wire ( ) connected to the diffusion layer area ( ) having the lower impurity concentration.

Method for forming a semiconductor device having contact wires of different sectional areas

A semiconductor device including an IGFET (insulated gate field effect transistor) ( ) is disclosed. IGFET ( ) may include a source/drain area ( ) having an impurity concentration distribution that may be formed shallower at a higher concentration than the impurity concentration distribution in another source/drain area ( ). A gate oxide film may include a first gate oxide film ( ) adjacent to source/drain area ( ) and a second gate oxide film ( ) adjacent to source drain area ( ). Second gate oxide film ( ) may be thinner than first gate oxide film ( ). An impurity concentration distribution of a second channel impurity area ( ) under second gate oxide film ( ) may be at a higher concentration than an impurity concentration distribution of a first channel impurity area ( ) under first gate oxide film ( ). In this way, an electric field at a PN junction of source/drain area ( ) may be reduced.

In fabrication of a semiconductor memory device and especially a DRAM (dynamic random access memory) having an HSG-type stacked-capacitor structure, after a storage-node-forming silicon film has been surface-treated with an HSG preprocess using dilute fluoric acid, the storage-node-forming film on the sidewall surface of a storage-node-forming contact pattern at an accessory or alignment region is prevented from floating in the air and hence being peeled off, which would have lowered the yield. For this purpose, the storage-node-forming silicon film covers the sidewall surface of the contact pattern at the alignment region.

Semiconductor memory device and method of manufacturing the same

In a semiconductor memory device with a stacked capacitor structure, a MOS transistor is formed on a substrate to have a gate electrode, a source region and a drain region. An insulating film is formed on the MOS transistor with an opening passing through the insulting film to one of the source and drain regions of the MOS transistor. A conductive storage electrode is formed such that it is connected to the one of the source and drain regions of the MOS transistor and has a first portion extending along a top surface of the insulating film and a second portion provided at each of edges of the first portion, and including a first subportion extending in an upper direction from an upper surface of the first portion and a second subportion below a lower surface of the first portion. Then, a capacitive insulating film is deposited and a conductive plate electrode film is deposited on the capacitive insulating film to complete a memory cell capacitor with the conductive storage electrode, the capacitive insulating film and the conductive plate electrode. The conductive storage electrode is formed by depositing a first conductive film on the insulating film and forming the first portion of the conductive storage electrode from the first conductive film, etching a surface portion of the insulating film where the first portion is not formed, and depositing a second conductive film and forming the storage electrode second portion from the second conductive film.

Semiconductor memory device with stacked capacitor structure

A method for fabricating a semiconductor device includes the steps of forming a MIS transistor, a contact hole, a sidewall insulating film, a first electrode, a dielectric film and a second electrode. The contact hole is formed by depositing a lower and an upper insulating film to cover the MIS transistor and selectively etching the insulating films to expose an upper surface of one of impurity diffusion layers serving as source/drain regions. The sidewall insulating film is formed by depositing an insulating material film using a material whose etching-back rate is different from that of the material for the upper insulating layer. The etching rate of the upper insulating layer is higher than that for the insulating material film. The etching-back under this etching condition results in the formation of the sidewall insulating film that projects upwardly from the surface of the upper insulating layer. With this configuration, it is possible to increase a surface area of the electrodes of a capacitor.

Method for fabricating semiconductor device having memory cell of

As a stack of a patterned film and an overlying conductor film, a conductor pattern is manufactured on an isolation layer of a semiconductor device by forming a two-film layer of a first conductor film and a semiconductor film, patterning the two-film layer in compliance with the conductor pattern into a patterned layer consisting of the patterned film and a semiconductor pattern and having a layer side surface, forming an insulator side wall on the side surface, etching away the semiconductor pattern, and selectively forming a second conductor film as the overlying conductor film. The side wall is used in preventing, when the second conductor film is selectively grown, undesirable lateral growth. Typically, the first and the second conductor films are made of aluminium to thicknesses of 200 and 400 nm and the semiconductor film, of polysilicon to a thickness of 400 nm.

Growing community of inventors

Tokyo, Japan

Kazutaka Manabe