Elpida Memory, Inc.

Ps4 Luxco S.a.r.l.

Kazutaka Koshiishi

Mitsuaki Katagiri

Satoshi Isa

Dai Sasaki

Haruo Akahoshi

A semiconductor device includes a package substrate, an IF chip, and a core chip. The package substrate has: first electrodes aligned and disposed on a first rear surface; second electrodes aligned and disposed in the first direction (Y direction) on a first front surface; and wiring that electrically connects the first electrodes and the second electrodes. The IF chip has third electrodes bonded to the second electrodes. The core chip is connected to the IF chip. In the first direction, the length of the IF chip is more than that of the core chip but equal to or less than that of the package substrate. One of the first electrodes is disposed further toward the outside than a core chip end portion in the first direction. At least one of the second electrodes is disposed further toward the outside than the core chip end portion in the first direction.

Semiconductor device

A semiconductor device includes a substrate having bumps on the backside thereof, a first semiconductor chip mounted on the surface of the substrate, a second semiconductor chip mounted on the first semiconductor chip above the surface of the substrate, a first bonding wire having a length Lfor connecting the first semiconductor chip to the substrate, a second bonding wire having a length L(where L&#x3e;L) for connecting the second semiconductor chip to the substrate, a first resin seal having a dielectric constant &#x2208;for sealing the first bonding wire, and a second resin seal having a dielectric constant &#x2208;(where &#x2208;&#x3c;&#x2208;) for sealing the second bonding wire. The relationship between the lengths Land Land the dielectric constants &#x2208;and &#x2208;is defined by an equation of &#x2208;=&#x2208;(L/L).

A semiconductor device is mounted on a package substrate which has a power supply line and a signal line formed of a normal or predetermined resistance material layer on a dielectric layer. A resistance material layer has a high resistance as compared with the normal resistance material layer and is additionally provided on the surface of the normal resistance material layer of the peripheral face of the signal line closest to the power supply line.

A high dielectric loss tangent layer is provided in a dielectric layer between a power-supply plane and a ground plane. The high dielectric loss tangent layer is arranged such that its edge is located between the edge of the power-supply plane and the edge of the ground plane. The edge of the high dielectric loss tangent layer is preferably separated by a predetermined distance or more from the edge of the power-supply plane or the edge of the ground plane which is located on the inner side.

Growing community of inventors

Tokyo, Japan

Kazutaka Koshiishi