Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Renesas Mobile Corporation

Kazushige Yamagishi

Takashi Miyamoto

Koyo Katsura

Mitsuru Watabe

Jun Satoh

Keisuke Nakashima

Kenichiroh Ohmura

Yasuhiro Nakatsuka

Jun Sato

Tetsuya Shimomura

Yoshihiko Hotta

Seiichi Saito

Yuichiro Morita

Yutaka Okada

Manabu Jyou

Atsushi Nakamura

Takashi Hotta

Shigeru Matsuo

Kazuyoshi Koga

Kenichiro Omura

A semiconductor device includes a one-segment tuner I/F that is connected to a one-segment tuner, a tuner I/F that is connected to a digital terrestrial tuner, a decoder that selectively decodes a first broadcast signal supplied from the one-segment tuner I/F and a second broadcast signal supplied from the tuner I/F, a general purpose processor that is provided separately from the decoder and decodes the first broadcast signal, and a switch unit that, based on signal intensity of the second broadcast wave, switches the decoding by the decoder between the first broadcast signal and the second broadcast signal while the general purpose processor is decoding the first broadcast signal. The one-segment tuner I/F, the tuner I/F, the decoder, the general purpose processor, and the switch unit are integrated on one chip.

Semiconductor device and signal processing method thereof

A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Data processing system and image processing system

The basic section of the multimedia data-processing system includes a CPU, an image display unit, a unified memory, a system bus, and devices, andconnected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unitand display control unit. Main storage areaand display areaare stored within the unified memory. Unified memory portfor connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

Memory access methods in a unified memory system

The basic section of the multimedia data-processing system includes a CPUan image display unita unified memorya system busand devicesandconnected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unitand display control unitMain storage areaand display areaare stored within the unified memory. Unified memory portfor connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

Data processing system having memory including mode register

The present invention can be introduced to an architecture such as a personal computer or an amusement equipment for realizing a high-speed graphic processing. In the case where a frame buffer, a command memory and an image processor are integrated in one chip in order to improve the drawing performance of an image processing device, each of the frame buffer and the command memory is constructed by a plurality of identical memory modules and the same row address is allotted to each memory module, thereby increasing the memory address depth. Thereby, it is possible to realize an incorporated frame buffer and an incorporated command memory each of which has a large capacity when seen from the image processor.

Data processing apparatus having DRAM incorporated therein

A memory controller is disclosed, in which upon receipt of an access request from a device, the memory controller activates a page designated by a row address of a first bank at a predetermined memory cycle, based on the access request. After that, before the read access to a page of the first bank, a second bank next to be accessed is precharged. In the case where a page mishit occurs due to the access from the first bank to the second bank by the graphic processing after the access to the first bank by the read operation, the memory controller activates the second bank immediately without precharging.

Memory controller

In order to assure that a plurality of circuits such as a CPU I/F circuit, a rendering circuit, a video input circuit and a display circuit, which are each required to always complete a processing within a prescribed time, are each assured the ability to make as many accesses to a memory as required to complete the processing within the prescribed time, it is necessary to arbitrate a contention for an access to the memory through an internal bus among the circuits by employing a bus control circuit wherein priority levels assigned to the circuits to make an access to the internal bus are dynamically changed by comparing degrees of access urgency among the circuits. In this way, circuits that each have to always complete theirs processing within a prescribed time are assured the ability to make as many accesses to the memory as required to complete the processing within the prescribed time even if a plurality of such circuits do exist.

Picture processing apparatus and picture processing method

A graphic processor including a rendering control circuit which carries out weighted averaging on pieces of pixel data of source image information arranged to form a pixel-data matrix corresponding to a pixel matrix with columns of the pixel-data matrix being oriented perpendicularly to a scanning direction in order to compute a weighted average of pieces of pixel data on rows of the pixel-data matrix adjacent to each other and on a column of the pixel-data matrix perpendicular to the scanning direction in so-called blend processing. The rendering control circuit reads out pieces of pixel data from the pixel-data matrix sequentially in a direction perpendicular to the scanning direction and computes a weighted average of the pieces of data. Image data subjected to blend processing is displayed by adopting an interlace scanning technique thereby eliminating undesired flicker.

Graphic processor and data processing system

Growing community of inventors

Higashimurayama, Japan

Kazushige Yamagishi