Fujitsu Corporation

Fujitsu Vlsi Limited

Kazushige Itazu

Eiji Fujine

Rieko Suzuki

Teruhisa Tsuyuki

Takako Murakami

Kiyoshi Saida

Takeshi Shimazaki

Kazunori Kawazoe

Yoshihiro Kamiya

Yukimi Nishiwaki

Yoshitaka Uchida

Takanori Nawa

Takayuki Matsuzawa

A program for generating layout data for a semiconductor integrated circuit analyzes a power network of individual modules in order to determine when an iterative layout process is complete. First, the individual modules are laid out and power supply wirings to the modules are laid out. Next, using cell size information about the cells within each of the modules, the cells of each module are temporarily arranged within the modules. Then, the power wirings and power supply terminals for each module are specified. A power network of each module is then sampled based on the cells, power wirings and power supply terminals of each module. Using the sample data, it is determined whether the modules and the power supply wirings to the modules need to be laid out again. The program may be executed on a CAD system.

Method and apparatus to optimize power wiring layout and generate wiring layout data for a semiconductor integrated circuit

According to the present invention, using a computer aided design system for designing semiconductor integrated circuits wherein a plurality of logic cells forming a circuit net are disposed on a semiconductor chip according to a net list specifying a connection pattern assigned among input and output terminals of a plurality of logic cells and a wiring length connecting the terminals.

Manufacturing method and apparatus of a semiconductor integrated circuit

Growing community of inventors

Kasugai, Japan

Kazushige Itazu