Fujitsu Corporation

Kazushi Sakamoto

Shoji Nakatani

Kenichi Sakai

Shigeaki Okutani

Tetsuro Okamoto

A vector data processing apparatus having a set of vector registers, one or more memory access pipelines, and one or more composite calculation pipelines, wherein the vector registers consist of a plurality of banks, and each bank is independently accessible. Each of the pipelines can cyclically access each of the banks of the vector registers when one or more of a predetermined number of time slots, through each of which time slots the access is carried out, are assigned to an instruction using the pipeline. Immediately when a memory access instruction is received, a vector unit control circuit, which controls operations of the vector data processing apparatus, assigns a time slot for a newly-detected memory access instruction using a memory access pipeline, if it is determined that the memory access pipeline is available based on the pipeline operation status flags, and that the time slot is available based on the detected status of the predetermined number of time slots. Further, when a composite calculation instruction is received, the vector unit control circuit assigns one or more time slots .for the newly-detected composite calculation instruction using a composite calculation pipeline, if it is determined that the composite calculation pipeline is available based on the pipeline operation status flags, and that time slots are available based on the detected status of the predetermined number of time slots.

Vector data processing apparatus wherein a time slot for access to a

A multiprocessor control system adapted to a multiprocessor system includes a switching circuit, a control stage circuit, a switching mode setting circuit, and a switching control circuit. The switching circuit selectively switches a second group of instructions supplied from first execution units to select the second group of instructions relating to one of the first execution units. The control stage circuit includes a plurality of register stages used for controlling a pipeline process. The control stage circuit sequentially stores the second group of instructions relating to the selected one of the first execution units in the register stages and outputs, for every register stage, a state indicating signal indicating state information regarding the corresponding register stage. The switching mode setting circuit generates a mode setting signal used for selecting one of a plurality of switching modes each defining a timing with which switching by the switching circuit occurs. The switching control circuit generates the switching signal based on the state indicating signals output from the control stage circuit and the mode setting signal indicative of one of the plurality of switching modes supplied from the switching mode setting circuit.

Multiprocessor control system for selectively executing vector

A vector access control system for a computer system is provided, including vector registers and a memory access pipeline function unit having an indirect address match checking circuit for detecting a coincidence between data of elements accessed by a plurality of indirect address data. An access to a main storage is carried out by adding a plurality of data, which are read from the vector registers and are necessary for an indirect address access, to a leading address. When a coincidence of data of elements and a resultant conflict between access requests to the main storage is detected by the indirect address match checking circuit, only a predetermined access request in the conflicting access requests is allowed.

Vector access control system

The present invention is a data processing system which has plural operation units which can execute plural instructions in parallel. The system also has plural instruction control units each of which comprises at least two stages, one for reading source operands from a local storage, and another for writing a resultant operand into the local storage. Each instruction control unit is provided with specific bank timing signals for accessing the local storage.

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Kawasaki, Japan

Kazushi Sakamoto