Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Socionext Inc.

Kazushi Kurata

Nobuo Higaki

Kazuya Furukawa

Shigeki Fujii

Tetsuya Tanaka

Tokuzo Kiyohara

Hideshi Nishida

Kozo Kimura

Hiroshi Kadota

Kunihiko Hayashi

Toshio Sugimura

Hideyo Tsuruta

Hiroyuki Morishita

Masanori Henmi

Masayuki Masumoto

Kousuke Yoshioka

A processor executes a plurality of tasks by switching a timeslot and iterating a plurality of timeslots. The processor includes a table in which tasks are defined in correspondence with timeslots. In the table, the number of timeslots to be held in one iteration is defined, for each of the timeslots a total time period during the predetermined number of iterations is designated, and a plurality of tasks are defined in correspondence with at least one of the timeslots. A timeslot is switched every time a predetermined period elapses. One task is selected and executed by referring to the table in correspondence with switching of timeslot.

Processor and program execution method capable of efficient program execution

A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

In a processor including a plurality of register groups, while a task is being executed using one of the register groups, a context of a task to be executed next is restored into another one of the register groups. If the execution of the task currently being executed is suspended before the restoration starts, the task execution is continued by using one of the register groups in which a context of a task executed previously remains and executing the task.

Task switching based on the execution control information held in register groups

A data transfer apparatus according to the present invention has; a DMAC and another DMAC which transfer data by direct memory access among a plurality of buses; a command queue which holds, as a queue, commands for instructing the data transfer; a bus information obtainment unit which obtains the commands from the command queue; a grouping unit which groups the held commands, based on a source and a destination designated in each of the obtained commands; a schedule unit which decides an order of issuing the commands sequentially from a group having more command, as a priority; and a selector which selects a command to be issued according to the decided order.

Data transfer apparatus, data transfer method, and program

The decoding apparatus in the present invention includes a memory operable to hold encoded data representing one of a compressed sound and a compressed image, a memory read-out unit operable to sequentially read out the encoded data from said memory, a match determining circuit operable to determine whether or not data matching a specific bit sequence exists in the encoded data read out by said memory read-out unit, a deleting circuit operable to delete a part of the specific bit sequence from the encoded data read out from said memory, when said match determining circuit determines that the specific bit sequence exists, and a decoding circuit operable to decode the post-deletion encoded data.

Decoding apparatus and encoding apparatus with specific bit sequence deletion and insertion

An interface unitassigns different SDRAMsandto adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for example, are issued alternately to the SDRAMsandto reduce waiting cycles resulting from the issue interval restriction. Furthermore, since individual clock enable signals CKEand CKEare output to the SDRAMsandso that burst transfers of the SDRAMsandcan be stopped individually, no cycle is necessary to stop the burst transfers.

DRAM controller for graphics processing operable to enable/disable burst transfer

The invention provides a data processing device with which disadvantages due to instruction allocation and decreased memory when adding a condition specifying field for executing conditional instructions can be prevented, and in which pipeline hazards due to the non-fulfillment of conditions can be suppressed when instructions with contradicting conditions are performed successively. The data processing device reads in and executes instructions in a certain sequence, and includes a fetch portion for reading in a computational instruction, a decoding portion for decoding the computational instruction that has been read in, an execution portion for executing the decoded computational instruction, and an instruction overriding control circuit that overrides, of one or a plurality of subsequent instructions that follow the computational instruction in said sequence and are associated with the computational instruction, all but one of the subsequent instructions, in accordance with an execution result of the computational instruction.

Data processing device that controls an overriding of a subsequent instruction in accordance with a conditional execution status updated by a sequencer

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Takatsuki, Japan

Kazushi Kurata