Hitachi, Ltd.

Hitachi Process Computer Engineering, Inc.

Hitachi Computer Electronics Co., Ltd.

Kazushi Kobayashi

Hitoshi Kawaguchi

Koichi Kimura

Tetsuya Mochida

Koichi Okazawa

Ichiharu Aburano

Takayuki Tamura

Hideki Kamimaki

Masami Jikihara

Hiroyuki Mano

Toshihiko Ogura

Hiroaki Aotsu

Hiromichi Enomoto

Kouichi Kimura

Hitoshi Suzuki

Tomohisa Kohiyama

Takeshi Igarashi

Shigeo Tsujioka

Hironori Oikawa

Hitoshi Sadamitsu

Kazumi Kubota

Goro Ohnishi

Naohisa Koizumi

Norihisa Amako

Kouichi Okazawa

Takeshi Aoki

Takanori Ishikawa

A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Bus system for use with information processing apparatus

An information processing apparatus is provided which is capable of carrying out the higher memory access. The information processing apparatus includes a memory unit of a synchronous DRAM device which serves to output data synchronously with the supplied clock signal, and a control unit for controlling the access to the memory unit in accordance with an instruction issued from a CPU. The clock signal which is to be supplied to the memory unit is outputted from the control unit. The clock signal which has been outputted from the control unit is supplied to the memory unit and also is pulled back to the control unit. The control unit fetches therein the data, which has been outputted from the storage unit, at the timing which is determined on the basis of the pulled back clock signal. As a result, the control unit reduces the difference between a delay of the data which is outputted from the control unit and a delay of the clock signal which is used to determine the timing at which the data is fetched therein.

Information processing apparatus

An apparatus for information display for displaying not only periodic information in accordance with schedule, but also non-periodic information regardless of the schedule, to passengers and passersby in stations, airports, harbors, bus terminals and streets, and the like. The apparatus comprises an information-storing section for storing a plurality of non-periodic information to be displayed regardless of the schedule, an input circuit for receiving a plurality of input signals transmitted from an external device or a remote place and display control section for simultaneously displaying the non-periodic information and periodic information which correspond to the kind of an input signal, when the apparatus receives this input signal from the external apparatus or the remote place. The apparatus may be a multi-screen display type having a plurality of screens. In this case, a combined screen data consisting of a non-periodic information and a periodic information can be displayed, or the non-periodic information or the periodic information can be displayed, on at least one of the screens.

Apparatus and method for information display

Information processing apparatus capable of reading data from memory at high speed

A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and controL buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controlling connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Multiple bus system using a data transfer unit

Growing community of inventors

Ebina, Japan

Kazushi Kobayashi