Seiko Epson Corporation

Kazuo Yazawa

Ryohei Tamura

Tomoyuki Shindo

Hironori Ota

A semiconductor chip housing tray that is used in a state of being stacked in a plurality of stages and houses a plurality of semiconductor chips, includes: a base plate; a plurality of upper surface protruding parts provided to an upper surface of the base plate and dividing the upper surface of the base plate into a plurality of first semiconductor chip housing areas; and a plurality of under surface protruding parts provided to an under surface of the base plate and dividing the under surface of the base plate into a plurality of second semiconductor chip housing areas. In the semiconductor chip housing tray, a margin width of the first semiconductor chip housing areas with respect to the semiconductor chips is smaller than a margin width of the second semiconductor chip housing areas with respect to the semiconductor chips.

Growing community of inventors

Suwa, Japan

Kazuo Yazawa