Nippon Electric Co., Ltd.

Nec Corporation

Matsushita Electric Industrial Co., Ltd.

Kazuo Tokuda

Hiroshi Minakuchi

Tokio Sawataishi

Mitsutoshi Sugawara

Masaki Ikeda

Shigeo Nishitoba

Shigeru Kagawa

Tatsuyuki Amano

Norio Terada

Masanobu Tsugita

Hidetaro Watanabe

A variable gain amplifier has a first amplifier circuit whose gain is A/n times (A being a real number excepting '0', and n being a real number larger than 1); a second amplifier circuit whose gain is A(n-1/n) times; level converter for level converting an output signal from the second amplifier circuit at a ratio corresponding to a level of a gain control signal having a predetermined level controllable range and at a ratio of 1/(n+1) at a central level within the level controllable range of the gain control signal; and an adder circuit for adding together an output signal from the level converter and an output signal from the first amplifier circuit at the ratio of 1:1. The variable gain amplifier has a gain controllable range of among 1/n.about.1.about.n times as the level of the gain control signal changes among the minimum level.about.the central level.about.the maximum level. When the gain of the second amplifier circuit is set to A(m-1/n) times (m being a real number larger than 1) and a level conversion ratio of the level converter is set to (1-1/n)/(m-1/n) at the central level of the gain control signal, the variable gain amplifer having the gain controllable range of among A/n.about.A.about.mA times is realized.

Variable gain amplifier

A stereo demodulation device includes an audio signal processing circuit, a muting circuit, a muting switch, and a variable resistor. At least a given signal processing function of the audio signal processing circuit is adjusted by supplying a control current from a control terminal thereof. The muting circuit outputs or blocks an audio signal processed by the audio signal processing circuit. A muting switch is commonly connected to a control terminal of the muting circuit and the control terminal for the given signal processing function of the audio signal processing circuit. The variable resistor adjusts the control current.

Stereo demodulation device

An oscillation circuit has a free-running oscillator operating at a predetermined frequency. A signal generator generates a trigger signal in synchronism with an input signal. The trigger signal is supplied to the free-running oscillator to bring the signal level in the oscillator to a reference level. The oscillator keeps its frequency even when there is no input signal, the frequency being approximately equal to an integer multiplied by the frequency of the input signal.

Oscillator synchronized to a pulse

In a signal processing device, such as a television receiver, a multiplex signal processing circuit with a switching device for selecting either a first image signal and a second image signal. A clamping circuit is provided for clamping the pedestal potential of the second signal at a reference voltage, a comparator compares the pedestal potential of the first signal with the reference voltage, and the pedestal potential of the first signal is equalized to the reference signal in accordance with the comparator output.

Signal processing unit

The present invention provides a transistor circuit suited for a synchronizing signal separator. More particularly, the transistor circuit can separate the noise-free synchronizing signal from a composite video signal. The transistor circuit comprises a transistor having an emitter coupled to an input terminal through a capacitor and to a constant current source, a base applied with a bias voltage and a collector connected to an output terminal, a comparator comparing the emitter voltage with a reference voltage, and means for turning the transistor off in response to the comparator output. A current charging circuit is preferably added.

Transistor circuit

A constant voltage generator capable of generating a constant voltage having a fixed temperature coefficient regardless of manufacturing errors is disclosed. The constant voltage generator comprises a transistor construction having a forwardly biased PN-junction, a Zener diode connected in series to an electrical path between the emitter and a collector of the transistor construction, a first resistor connected between a base and the emitter of the transistor construction, and a second resistor connected between the base and the collector of the transistor construction. The transistor construction, the Zener diode and the first and second resistors are all formed in a common semiconductor substrate, the first resistor being composed of a region of one conductivity type and the second resistor being composed of a pinch resistor formed in the substrate. The transistor and Zener diode may be composed of a first semiconductor region of one conductivity type, a second region of the other conductivity type formed in the first semiconductor region and a third region of the one conductivity type being formed in the second region. The first region may be composed of a fourth region of the other conductivity type formed in the first semiconductor region, and the second resistor may be composed of a fifth region of the other conductivity type formed in the first semiconductor region and operable as a resistive region and a sixth region of the one conductivity type covering a part of the fifth region.

Constant voltage generator for generating a constant voltage having a

A transistor circuit having a plurality of constant current sources wherein a compensating resistor of a predetermined value is inserted between the base of the transistor of one of the constant current sources and a reference voltage supply terminal. The compensating resistor serves to equalize the current variation between currents flowing through first and second resistive loads and thereby equalizes D.C. circuit output potentials for the circuits being driven by the constant current sources. This equalization is achieved irrespective of variations in transistor current gain due to temperature fluctuation or manufacturing error.

Transistor circuit having a plurality of constant current sources

An automatic speed control circuit for an electric motor is provided with a d.c. amplifier circuit having an output transistor of npn type. The motor is driven by a control signal supplied from the collector of the output transistor to control the motor speed. The collector of the output transistor is connected to one terminal of the electric motor, while another terminal of the motor and the emitter of the output transistor are respectively coupled to the positive and the negative terminals of a d.c. power source. The control signal supplied from the output transistor to the motor is changed in compliance with any variation of the power source. Therefore, the motor speed is independent of any variation of the power source.

Control circuit of an electric motor comprising an output transistor of

A circuit for producing an error voltage for a negative feedback loop for automatic control of a motor speed comprises a monostable multivibrator triggered by a feedback signal of a frequency representative of the motor speed for generating a rectangular signal of a predetermined pulse width, a pulse height proportional to a source voltage for the multivibrator, and a duty cycle decided by the frequency. A potentiometer-integrator derives a variable voltage proportional to an average of the rectangular signal voltage. A potential divider for the source voltage derives a reference voltage indicative of a desired motor speed. A comparator derives a difference between the variable and reference voltages as the error voltage.

Circuit for producing for a feedback motor speed control loop an error

A gain controllable amplifier of the present invention comprises a first and a second differential amplifier. The first differential amplifier serves as an amplifier for an input signal to be impressed on emitters connected in common with each other, while the second differential amplifier serves as a base bias voltage control circuit of the first differential amplifier. The bias voltage derived from the second differential amplifier is changed by a D.C. bias voltage applied to the bases of the respective transistors in the second differential amplifier. The connected to the respective output terminals of the second differential amplifier are transistors whose bases receive a constant voltage. The gain of the first differential amplifier can be controlled by adjusting the D.C. bias voltage applied to the second differential amplifier. The present invention further comprises two current supply circuit each connected to the aforesaid respective output terminals of the second differential amplifier. When one of the transistors in the second differential amplifier is brought into a cut-off condition, the base bias voltage on the first differential amplifier is supplied directly through a current supply circuit. As a result, a variable range of the base voltage on the second differential amplifier is becomes wider, with a resulting increase in the gain control range of the first differential amplifier, thereby achieving increased attenuation of gain. The amplifier according to the present invention is suited for use as a gain control circuit especially for an audio circuit which requires attenuation to a great degree.

Amplifier with gain control means

A pulse generating circuit which normally draws no current in the absence of a trigger pulse is disclosed. The circuit generates a pulse having a constant width independent of temperature or power supply voltage variations in response to a trigger pulse. The pulse width is determined by an RC time constant and the ratio of a resistive voltage divider.

Circuit for transforming a trigger signal into a pulse

A trigger pulse generator circuit for converting an input pulse into a sharp pulse to be used as a trigger pulse is disclosed. The input pulse is applied to a first and a second switching means which are connected in cascade, the second switching means having a larger delay time than that of the first switching means. An output trigger pulse is derived from a connecting point of the first and second switching means. The first switching means becomes cut-off in response to the removal of the input pulse, while the second switching means becomes cut-off a predetermined time after the removal of the input pulse due to a time delay caused by the storage time of a transistor of the second switching means. In consequence, a sharp trigger pulse is derived from the output terminal. Preferably, a discharging means for the charge stored in the second switching means is further provided between the ground and the second switching means. This trigger pulse generator circuit is advantageous in that no capacitive element is necessitated, and so it is quite suitable for application to an integrated circuit.

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Tokyo, Japan

Kazuo Tokuda