Fujitsu Corporation

Kazuo Tanimoto

Setsuo Kurafuji

A memory circuit has a decoder circuit for receiving address signals and generating word designating signals. The decoder circuit has a plurality of decoder circuit blocks and includes a circuit for receiving some of the address signals and generating signals designating one of the decoder circuit blocks, whereby the current flowing in each of the decoder circuit blocks is reduced as long as the blocks are not designated.

Memory circuit having a decoder

A static memory circuit incorporating memory cells of a MOS static type comprising a plurality of potential setting circuits for setting the ground side potential of one selected memory cell to be lower than those of other non-selected memory cells. Thus, reducing power dissipation by reducing current flowing through half-selected and non-selected memory cells without reducing read speed.

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Tama, Japan

Kazuo Tanimoto