Sony Corporation

Kazuo Taniguchi

Masaharu Yoshimori

Yuji Yamaguchi

Masayuki Miyabayashi

Hiroyuki Ozawa

Atsushi Tamura

Goragot Wongpaisarnsin

Ryohei Iida

A shared memory device capable of simplifying wiring to a memory, preventing a decline of performance due to an increase of the area and long wiring, and improving extensibility of scalability of the system is provided: wherein the device has a plurality of memory systems each including a memory macro, a processor, and a memory control unit for controlling an access to a memory macro; wherein the memory control unit of each of the memory systems transfers information between the processor and memory macro and transfers information with a memory control unit of a different memory system; the memory macro of each of the memory systems has a memory interface capable of transferring data; and the memory interfaces of the memory macros of different memory systems are mutually connected.

Shared memory device

A semiconductor memory enabling a read modify write operation of data, comprising: a memory cell array including a plurality of memory cells arranged in a matrix and able to be written with and read out data; a read address decoding means for independently decoding an address of a read memory cell in response to a read address; a write address decoding means for independently decoding an address of a write memory cell in response to a write address; a data reading means for reading data of a memory cell addressed by the read address decoding means; a data writing means for writing data to a memory cell addressed by the write address decoding means; and an address delay means by which a write address decoded by the write address decoding means is delayed by a predetermined time from a read address decoded by the read address decoding means, wherein the predetermined time is set as a predetermined plurality of times of basic synchronization pulse periods so that the data read modify write operation is accomplished in a pipeline manner by the basic synchronized pulse.

Method and circuit for enabling a clock-synchronized read-modify-write operation on a memory array

A logic IC including an embedded memory is provided with a test circuit therein which allows the embedded memory to be tested by using only three additional external pins of the logic IC for test purposes without regard to the bit count of a unit in which data is written into or read out from the embedded memory. In addition, the embedded memory can be tested by adopting a method that requires a period of testing time shorter than the related art one.

Test circuit and test method for semiconductor memory

A system for mapping texture data at high speed with flexibility to different applications wherein texture data is sent to a memory interface (MEMIF) thorough a digital differential analyzer (DDA) and a texture mapping unit (TMAP) and loaded to free areas of a Z coordinatory memory (ZBUF) and a drawing data memory (FBUF). A Z coordinate value or drawing data is read/written through a bidirectional port. The TMAP converts texture coordinates into a physical address, reads texture data from dedicated read ports of the ZBUF and the FBUF with the physical address, and maps the texture data. Each of the ZBUF and the FBUF has a DRAM unit and an auxiliary memory. Data of one row of the DRAM unit can be sent to the auxiliary memory means at a time. When desired texture data is not present in the auxiliary memory, data of the entire row of the desired texture data is sent to the auxiliary memory and then read.

Apparatus and method for storing and accessing picture generation data

Method and circuit for enabling a clock-synchronized read-modify-write

A semiconductor memory comprising a memory cell array including a plurality of the memory cells arranged in a matrix, the memory cells being able to be written with and read out data; a reading/writing means for reading and writing data with respect to a selected memory cell; a plurality of auxiliary data storing means arranged in series, a first means among them being connected to the memory cell array and each of the auxiliary data storing means storing a part of the data stored in the memory cell array; a plurality of data output means, each of the data output means being connected to one of the auxiliary data storing means; and a plurality of external data buses, each of the external data buses being connected to one of the data output means; each of the data output means being able to independently output the data stored in a corresponding auxiliary data storing means to a corresponding external data bus.

Growing community of inventors

Kanagawa, Japan

Kazuo Taniguchi