Canon Kabushiki Kaisha

Renesas Electronics Corporation

Hitachi, Ltd.

Fujitsu Corporation

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Other

Oki Electric Industry Co., Ltd.

Nippon Telegraph and Telephone Corporation

Hitachi-kokusai Electric Inc.

Kokusai Electric Co., Ltd.

Nec Corporation

Bridgestone Corporation

Hoya Corporation

Hitachi Vlsi Engineering Corp.

Kazuo Tanaka

Shunsuke Toyoshima

Hiroyuki Mizuno

Manabu Miyamoto

Rie Nishiyama

Naozumi Morino

Kazuo Sakamoto

Takahiro Hayashi

Keiji Ikemori

Sadahiko Tsuji

Toshio Yamada

Masatake Kato

Takeo Toba

Hideto Yamaguchi

Hiroyasu Ishizuka

Noboru Koumura

Yukichi Niwa

Masaaki Ueno

Ryusho Hirose

Yasuo Ogino

Mitsutoshi Ohwada

Nobuyuki Nemoto

Taro Asao

Kazunori Horachi

Haruo Nozaki

Toshihiko Irie

Yusuke Kanno

Tsunefumi Tanaka

Shigeyuki Suda

Masashi Sugishita

Tohru Kobayashi

Muneharu Sugiura

Kenzo Urabe

Masato Hamamoto

Yukihiro Ozeki

Takafumi Inoue

Hideaki Satoh

Hiromasa Katoh

Masaru Iwabuchi

Tatsuya Ninomiya

Toshihiro Suzuki

Atsushi Shimizu

Hirotaka Nishizawa

Akihiro Fujiwara

Atsuo Watanabe

Tomoki Watanabe

Michio Nagai

Takehiko Kiyohara

Kazuya Matsumoto

Kazuo Naito

Takahide Ikeda

Tetsuro Kuwayama

Noritsugu Hirata

Toshio Honda

Akinobu Watanabe

Mitsuhiro Tokuhara

Manabu Suzuki

Kazuhiro Hayakawa

Youichi Okuno

Satoru Isomura

Tetsuo Sueda

Akira Tajima

Minoru Nakano

Shinobu Sugiura

Nobuo Tamba

Toshiyuki Kikuchi

Setsuo Akiyama

Yasushi Fukuda

Kenji Shirako

Toshiro Hiramoto

Mikinori Kawaji

Masami Usami

Yuko Ito

Takafumi Oka

Miwa Taniguchi

Takayuki Yoshitake

Katsumi Kishida

Kunio Takeshi

Hirotaka Shikada

Eiji Shimose

Masayuki Sugizaki

Hisanobu Monobe

Toru Koizumi

Hiroyuki Matsumoto

Aiichiro Koyama

Tatsuo Suzuki

Nobuyoshi Aida

Seiichiro Azuma

Masafumi Asano

Kunio Takesi

Tomoaki Kawamura

Hiroshi Nagaoka

Yusuko Kanno

Masaaki Ohkubo

Toshi Takajo

Sukehiro Yoshida

Sinmei Hirano

Yasusi Sekine

Toru Nakagawa

Atsushi Takeshita

An information processing apparatus comprises a first heat generation circuit, a second heat generation circuit, a blocking assembly, and a processor. The blocking assembly performs a first operation of blocking air flowing from the first heat generation circuit toward the second heat generation circuit or a second operation of passing the air, and the processor is configure to instruct the blocking assembly to perform the first operation in a case where a temperature of the air is higher than a predetermined value, and instruct the blocking assembly to perform the second operation in a case where the temperature of the air is lower than the predetermined value.

Information processing apparatus and cooling method

A semiconductor integrated circuit device with a 'PAD on I/O cell' structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor chip. When seen in a plan view of the I/O part, a resistance lies above the transistor and a first and a second diode lie above the resistance; a second transistor lies above the diodes; and a logic block lies above the second transistor with a pad lead part, for example, formed in a metal wiring layer, therebetween. This permits the pad through the second transistor to be on the same node and therefore the pad lead part can be disposed almost in the center of the I/O part.

Semiconductor integrated circuit device having an NMOS with a high resistance drain terminal

The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Semiconductor device

Provided is a substrate processing apparatus capable of suppressing inferiority when heat treatment is controlled using a temperature sensor. The substrate processing apparatus includes a heating means configured to heat a process chamber wherein a substrate is accommodated; a first temperature detection means configured to detect a temperature about the substrate using a first thermocouple; a second temperature detection means configured to detect a temperature about the heating means using a second thermocouple; a control unit configured to control the heating means based on the temperature detected by the first temperature detection means and the temperature detected by the second temperature detection means; and a control switching means configured to control the control unit based on the temperatures detected by the first temperature detection means and the second temperature detection means such that the control unit is switched between a first control mode and a second control mode, wherein a heat resistance of the first thermocouple is greater than that of the second thermocouple, and a temperature detection performance of the second thermocouple is higher than that of the first thermocouple.

Substrate processing apparatus capable of switching control mode of heater

A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region.

Semiconductor integrated circuit device

Semiconductor device with output circuit and pad arrangements

Semiconductor devices with output circuit and pad

Semiconductor device with output circuit and pad

In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit

Semiconductor device with output circuit arrangement

A pull-up circuit prevents generation of a leak current if a difference of potentials occurs between a power source voltage of a pull-up circuit (a bus-hold circuit) and an input terminal. A control terminal is provided in the bus-hold circuit. Inputs of the input terminal and the control terminal are input to a NOR gate, and an output of the NOR gate is input to a gate terminal of a first MOSFET that controls coupling between an input terminal and the power source voltage of the bus-hold circuit. A second MOSFET ('control' MOSFET) is provided as a switch that operates by an inverted output of the control terminal. By coupling the first MOSFET and the control MOSFET in series, the coupling between the input terminal and the power source voltage is controlled with a higher precision, thereby preventing generation of a leak current.

Semiconductor device and method of controlling the same

The present invention comprises a CHAwhich transmits/receives data to/from an external device, a DKAwhich transmits/receives data to/from an HDD unit, a primary cache unitwhich has a primary cache memory, a secondary cache unitwhich is installed between the primary cache unitand the DKAand has a secondary cache memory, a CCPwhich stores write target data received by the CHAin the primary cache memory, and a CCPwhich stores the write target data in the secondary cache memory, and transfers the write target data stored in the secondary cache memoryto the DKA

Storage system and data management method

To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.

A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.

Semicondutor integrated circuit device

Growing community of inventors

Tokyo, Japan

Kazuo Tanaka