Sanyo Electric Co., Ltd.

Kazuo Takeda

Nobuyuki Sekikawa

Nobuo Itoh

Tadayoshi Takada

Toshimasa Sadakata

Teruo Tabata

Yoshiaki Sano

Chikao Fujunuma

Tetsuya Kubota

Yasuhiro Tamada

Katsuhiro Hayasaka

A method of making a semiconductor integrated circuit provided with an isolating region constituted of an upper and lower isolating regions, and integrated circuit element regions is disclosed, wherein: the lower isolating region is diffused upward to a depth of a little more than half the thickness of an epitaxial layer to link with the upper isolating region prior to a doping of the upper isolating region; the doping of the lower isolating region and integrated circuit element regions, is implemented by means of ion implantation through a resist film which is capable of blocking ions implanted and in which specified doping windows have been formed in advance, and a SiO.sub.2 film is used as a reference mask in an ion implanting step, and the respective borders of the upper isolating region and the specified regions of the circuit elements is determined by self-alignment. The method has advantages that the upper isolating region can be prepared by heat-treatment for relatively short time, reducing lateral diffusion and the occupied area thereof, and slippage by masking is remarkably reduced, providing a semiconductor integrated circuit with high density.

Method for manufacturing a semiconductor integrated circuit

A method of fabricating a semiconductor integrated circuit comprises the steps of: forming buried layers in predetermined regions of a semiconductor substrate; forming an epitaxial layer covering the substrate and the buried layers; forming isolation regions dividing the epitaxial layer into a plurality of islands; selectively implanting ions to form a base region of a vertical bipolar transistor in a surface layer of one island and simultaneously to form a resistor region in a surface layer of another island; and selectively diffusing impurities into a surface layer of the base region, to form an emitter region of the vertical bipolar transistor.

Method of fabricating a semiconductor integrated circuit

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Gunma, Japan

Kazuo Takeda