Fujitsu Corporation

Kazuo Sumitani

Yoso Igi

Fumiaki Tahira

Keiko Kawasaki

Kenji Fujisono

A memory apparatus including a back board having a lower address side and an upper address side, and a plurality of memory cards installed on the back board. Each memory card comprises a lower address side detecting signal pin for determining whether that memory card is installed on the lower address side of the back board, capacity detecting signal pins for notifying other memory cards of the capacity of that memory card, address signal pins, connected to an address signal line, and an address assigning circuit. When a memory card is installed on the lower address side of the back board, the capacity detecting signal pins and address signal pins assign an address to that memory card starting from a minimum address on the lower address side, and assign and address to another memory card which is installed on the upper address side starting with an address following the maximum address of the memory card installed on the lower address side.

Memory apparatus comprising memory cards with a side detecting signal

A communication control device includes a transmission speed converting unit having a dual port video RAM containing a RAM and a SAM, and a control unit having a register for storing a data store leading address of the RAM, a register for setting the number of words stored in the SAM, and a CPU. When data are transmitted, a user issues a data transmission request to the CPU in the control unit. According to the request, the CPU reads data from one system at its data transmission speed to the RAM or the SAM of the dual port video RAM, internally transmits the data between the RAM and the SAM, and finally transmits the internally transmitted data to the other system at its data transmission speed. The dual port video RAM absorbs the difference between the data transmission speeds of these two systems, and permits the data transmission at a lower cost than when using a FIFO memory and at a higher speed than when using a buffer memory.

Communication control system

A bus control system for controlling intermultiprocessor communication by polling, comprising a listener response signal line for transferring an end answer signal from a listener circuit to a talker circuit immediately when the transfer of data between the talker and the listener is finished, without waiting for the completion of data transfer within the receiving processor, whereby the bus occupation period is shortened.

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Kawasaki, Japan

Kazuo Sumitani