Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Kazuo Shimokawa

Kazuhito Higuchi

Susumu Obata

Mitsuo Sano

Keiichiro Matsuo

Takashi Koyanagawa

Akihiko Happoya

Akira Tojo

Takayuki Tajima

Hisashi Ito

Tatsuya Yamada

Takashi Ito

Yoshiki Endo

Osamu Usuda

Masahiro Urase

Yoshiaki Sugizaki

Akihiro Kojima

Tatsuya Kobayashi

Masayuki Uchida

Takeshi Miyagi

Taizo Tomioka

Akiya Kimura

Tomoyuki Kitani

Toshiya Nakayama

Masatoshi Tanabe

Akio Nakagawa

Ichiro Omura

Yusuke Kawaguchi

Masaki Toyoshima

Kenichi Matsushita

Tomohiro Iguchi

Hiroshi Koizumi

Noriaki Yoshikawa

Tomomichi Naka

Izuru Komatsu

Yasuhito Saito

Michinobu Inoue

Hiroshi Takei

Yasuhide Okada

Haruki Arai

Morio Takahashi

Toshihisa Inoue

Kazuhiko Kurahashi

Masako Ooishi

Taiki Miura

Tomohiro Kawano

Hideaki Fukuzawa

Hideto Furuyama

Yoichiro Kurita

Michiko Hara

Kei Masunishi

Miyoko Shimada

Keiju Yamada

Akira Ushijima

Yusaku Asano

Yasunari Ukita

Mikiya Iida

According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer therebetween, and first and second internal electrodes. The substrate has first and second main surfaces. One partial region of the first main surface is provided with first recesses. A region of the second surface corresponding to a combination of the one partial region and another partial region is provided with second recesses. The conductive layer covers the main surfaces and side walls and bottom surfaces of the recesses. The first internal electrode is provided on the one partial region and electrically connected to the conductive layer. The second internal electrode is provided on the another partial region and electrically connected to the substrate.

Capacitor and etching method

A semiconductor device includes an insulating layer, a conductive member provided inside the insulating layer, a chip disposed on a first surface of the insulating layer and connected to the conductive member, and an electrode connected to the conductive member via a barrier layer. A resistivity of the barrier layer is higher than a resistivity of the conductive member. At least a portion of the electrode protrudes from a second surface of the insulating layer.

Method for manufacturing semiconductor device having chip stacked and molded

According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, and a dielectric layer. The conductive substrate has a first main surface and a second main surface and is provided with a plurality of recesses on the first main surface. The conductive substrate is further provided with a plurality of holes in one or more portions each sandwiched between two adjacent ones of the recesses such that a region on a side of the first main surface has a larger porosity than a region on a side of the second main surface. The conductive layer covers the first main surface, side walls and bottom surfaces of the recesses, and walls of the holes. The dielectric layer is interposed between the conductive substrate and the conductive layer.

Capacitor

A wire bonding apparatus according to an embodiment bonds a wire to a bonding portion by generating an ultrasonic vibration in a state of pressing the wire onto the bonding portion. The wire bonding apparatus includes a bonding tool that causes the wire to contact the bonding portion and applies a load, an ultrasonic horn that generates the ultrasonic vibration, a load sensor that continuously detects the load applied from the bonding tool to the bonding portion, and a controller that controls the operation of the bonding tool and the ultrasonic horn. The controller analyzes data of the load output from the load sensor between when the wire contacts the bonding portion and when the ultrasonic vibration is generated, and controls the operation of the bonding tool and the ultrasonic horn based on an analysis result.

Wire bonding apparatus and wire bonding method

A structural body according to an embodiment includes a conductive substrate. A main surface of the conductive substrate includes a first region and a second region adjacent to the first region and lower in height than the first region. The first region is provided with one or more recesses having a bottom, a position of which is lower than a position of the second region. A surface region of the conductive substrate on a side of the main surface includes a porous structure at a position between the second region and the one or more recesses.

Structural body and method of manufacturing the same

According to one embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer, and first and second external electrodes. The conductive substrate has a first main surface provided with recess(s), a second main surface, and an end face extending between edges of the first and second main surfaces. The conductive layer covers the first main surface and side walls and bottom surfaces of the recess(s). The dielectric layer is interposed between the conductive substrate and the conductive layer. The first external electrode includes a first electrode portion facing the end face and is electrically connected to the conductive layer. The second external electrode includes a second electrode portion facing the end face and is electrically connected to the conductive substrate.

Capacitor and capacitor module

According to an embodiment, a capacitor includes a conductive substrate, a conductive layer and a dielectric layer. The conductive substrate has a first main surface and a second main surface. The first main surface includes sub-regions. Each sub-region is provided with recesses or projections each having a shape extending in one direction and arranged in a width direction thereof. One or more of the sub-regions and another one or more of the sub-regions are different from each other in a length direction of the recesses or protrusions. The conductive layer covers sidewalls and bottom surfaces of the recesses or sidewalls and top surfaces of the projections. The dielectric layer is interposed between the conductive substrate and the conductive layer.

A semiconductor device includes a redistribution layer, a bump bonded to a first surface of the redistribution layer, and a chip bonded to a second surface of the redistribution layer. The redistribution layer includes an insulating layer, a conductive member connecting the bump to the chip and being provided inside the insulating layer, a bonding electrode connected between the conductive member and the bump, and a conductive layer provided between the insulating layer and the conductive member and between the bonding electrode and the conductive member. A resistivity of the conductive member is lower than a resistivity of the conductive layer.

Semiconductor device and method for manufacturing same

Semiconductor device having chip stacked and molded

According to an embodiment, a method of forming a porous layer includes forming a porous layer containing a noble metal on a surface made of a semiconductor by displacement plating. The plating solution used in the displacement plating contains a noble metal source, hydrogen fluoride, and an adjusting agent adjusting a pH value or zeta potential. The noble metal source produces an ion containing the noble metal in water. The plating solution has a pH value in a range of 1 to 6.

Etching method and plating solution

According to one embodiment, in a processing system and determining method, a X-ray intensity of character X-rays generated by irradiating a catalytic layer of a noble metal formed on a surface of a substrate with X-rays is detected. In the processing system and the determining method, either the detected X-ray intensity or a parameter calculated using the X-ray intensity is obtained as a determination parameter. In the processing system and the determining method, based at least on the determination parameter, whether or not the catalytic layer has been formed into a state suitable for etching the surface of the substrate is determined.

Processing system for a catalytic layer of a noble metal formed on a surface of a substrate

An etching method according to an embodiment includes forming an uneven structure including a projection on a surface of a semiconductor substrate; forming a catalyst layer including a noble metal on the surface selectively at a top surface of the projection; and supplying an etchant to the catalyst layer to cause an etching of the semiconductor substrate with an assist from the noble metal as a catalyst.

Etching method, method of manufacturing semiconductor chip, and method of manufacturing article

A semiconductor device includes a base, a first semiconductor chip mounted on the base, and a second semiconductor chip provided above the first semiconductor chip. The second semiconductor chip includes a first portion, a second portion including a region directly above a center of the first semiconductor chip, and a third portion including part of a portion of the second semiconductor chip other than a region directly above the first semiconductor chip. The second portion is thicker than the first portion. The third portion is thicker than the second portion and is disposed at a position sandwiching the first semiconductor chip.

Semiconductor device and method for manufacturing semiconductor device

Growing community of inventors

Yokohama, Japan

Kazuo Shimokawa