Nec Corporation

Other

Tokyo Electron Limited

Nippon Steel Corporation

Covalent Materials Corporation

Kazuo Shibata

Masahiko Yamamoto

Teruo Iwata

Toshio Komuro

Manabu Amikura

Katsumi Nishikawa

Hiroo Kawasaki

Kenshi Katayama

Koji Fujikawa

To provide a plane heater, including a carbon wire heating element CW, in which surface arrangement density of the heating element CW in an outer area is denser than that in an inner area. A power supply terminal unit having connection wires for supplying electricity to the heating element CW is arranged in the center on the back side of a silica glass plate-like member. Connection wiresandconnected with the heating element CW in the inner area are connected with the heating element in the inner area in the center of the silica glass plate-like member. Connection wiresandconnected with the heating element in the outer area are extended from the center of the silica glass plate-like member toward the outer area and connected with the heating element CW in the outer area, without intersecting the heating element CW in the inner area.

Plane heater

A method and apparatus for generating a test pattern enabling the detection of malfunctions produced when a semiconductor device is loaded on actual equipment prior to marketing. Using a logical analyzer, signal waveform data collected during the period of signal malfunction is acquired. This signal waveform data is converted by a test pattern generating device into a test pattern for automatic testing equipment. This test pattern is used to change data at the time of malfunction into normal data to generate a pattern of expected values for an output signal of the semiconductor device. Then, it is determined whether the input signal setting required for an output signal of the semiconductor device is present in the signal waveform data. If not, a test pattern for setting the input signal is generated. If the malfunction is reproduced in the testing equipment, the test pattern is used as a mass production test.

Semiconductor device testing method and system employing trace data

A design drawing transmission system comprises a design drawing transmission device including a scanner for reading a design drawing drafted on a recording sheet and a transmitter for transmitting drawing information including the image signal prepared by the scanner through a predetermined path, and a design drawing receiving device including a receiver for receiving the drawing information transmitted through the transmission path, a memory for storing the drawing information received by the receiver and a plotter for reading out the drawing information stored by the memory and reproducing the design drawing on a recording sheet on the basis of the image signal included in the drawing information.

Design drawing transmission system

An intermediate voltage generator incorporated in a dynamic random memory device is shared between digit lines and counter electrodes of storage capacitors forming parts of memory cells, and supplies an intermediate voltage through precharging transistors to digit lines already shifted to high low voltage levels and directly to the counter electrodes, wherein a switching transistor cuts off the voltage propagation path between the intermediate voltage generator and the precharging transistors in the precharging stage so that the storage capacitors are free from voltage fluctuation due to the precharging operation on the digit lines.

Dynamic random access memory device with precharging unit preventing

A circuit for carrying out ordinary 'write' and 'read' operation during operation of applying a test voltage to a cell opposite electrode in test operation is provided. The circuit converts a test mode instruction signal to an ordinary operation instruction signal in a semiconductor memory device. The test mode instruction signal can be applied to an input pin of the semiconductor memory device, so that the test operation can be carried out even after the assembly of the semiconductor memory device.

Semiconductor memory device

A signal generating circuit which generates an output signal in a dynamic manner without being influenced by noise is disclosed. The signal generating circuit comprises a first transistor connected between a power voltage source and an output node, and second and third transistors connected in series between the output node and a ground voltage line. A first signal which assumes an active level in a first period and an inactive a second period subsequent to the first period, is applied to a gate of the second transistor, and a second signal which assumes an active level for a first time duration in the second period and an inactive level in a remaining second time duration in the second period and the first period, is applied to a gate of the first transistor. A third signal which assumes an active level in the first period and an inactive level in the second time duration, is applied to a gate of the second transistor.

Signal generating circuit free from malfunction based on noise

An improved boot-strap type signal generating circuit with a small input capacitance and operable with a minimum delay time is disclosed. The signal generating circuit employs a buffer circuit responsive to an input signal for generating a buffered signal and an inverting delay circuit. The buffered signal is applied to one end of a capacitor connected to a gate of an output field effect transistor and also to an input of the inverting delay circuit. The output of the inverting delay circuit is used to control a potential of the other end of the capacitor.

Growing community of inventors

Tokyo, Japan

Kazuo Shibata