Renesas Technology Corp.

Kazuo Nomura

Yutaka Takikawa

Koichi Kawauchi

Kazuyuki Kawamoto

Nobutaka Imanishi

Satoko Kamakura

Rie Matsuo

A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction.

Semiconductor memory

A data slicer of the present invention comprises a reference voltage generation circuit and a comparator. The reference voltage generation circuit comprises a plurality of capacitances which area connected in parallel to one another, holding electrical charges on the basis of an input signal, a plurality of first switches which are connected to the plurality of capacitances with first nodes, respectively, for controlling the inflow of the input signal to the plurality of capacitances and a plurality of second switches which are connected to the plurality of capacitances with the first nodes, respectively, for controlling the connection among the plurality of capacitances. The plurality of first switches are controlled with predetermined timing where these first switches are individually brought into an ON state, and the plurality of second switches are controlled with predetermined timing where all the second switches are brought into an ON state. With this construction, the present invention is intended to provide a data slicer which comprises a reference voltage generation circuit capable of generating an appropriate slicer reference voltage even if the input signal quickly changes.

Data slicer for generating a reference voltage

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Hyogo, Japan

Kazuo Nomura