Adv Antest Corporation

Takeda Riken Kogyo Kabushiki Kaisha

Kazuo Noguchi

A state analysis section which loads first input data into a first data memory for each change in state of the data and a timing analysis section which loads second input data into a second data memory with a fixed period are provided. The loading intervals of the first input data are measured by a data interval measuring circuit and each measured data loading interval is stored in a data loading interval memory. When the first and second input data are detected to match preset data in first and second trigger detectors, respectively, the detected outputs are delayed by first and second delay means, and by the outputs of the first and second delay means, the first and second data memories are stopped from the data loading thereinto. The time difference between the stopping of the data loading into both the data memories is measured by a time difference measuring circuit and the measured time difference is stored in a time difference memory. When one of the data stored in one of the first and second data memories is specified by specifying means, data in the other data memory corresponding to the point of time at which the specified data was loaded is detected using the data loading intervals stored in the data loading interval memory and the time difference stored in the time difference memory.

Logic analyzer

Logic data (input data) is sequentially supplied to a data memory using sampling pulses and the input data is written into the data memory at an address specified by an address signal from an address counter which advances by one upon each occurrence of the sampling pulse. The input data and an output trigger word from a trigger word register are compared by a trigger word detector, and when coincidence is detected therebetween, a coincidence signal is generated, which signal is delayed by a delay circuit by a value corresponding to output delay data from a delay register. The delayed output is provided as a stop signal. By the stop signal the address counter is preset to a leading address of a storage area of the data memory into which data is to be stored and the next trigger word is provided from the trigger register. Further, the next delay data is provided from a delay register and the next store number is output from a store-number register. The sampling pulses are counted by a store-number counter, and when the count value coincides with the output store number from the store-number register before the stop signal is generated, the address counter is preset to the leading address of the storage area of the data memory into which data is being written at that time.

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Kumagaya, Japan

Kazuo Noguchi