Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Other

Elpida Memory, Inc.

Nagoya University

Hitachi Europe Limited

Kazuo Nakazato

Kiyoo Itoh

Toshikazu Shimada

Hiroshi Mizuta

Hideo Sunami

Toshiyuki Mine

Hideyuki Matsuoka

Masahiro Moniwa

Ken Yamaguchi

Hiroshi Kujirai

Haroon Ahmed

Tatsuya Teshima

Tsuyoshi Tabata

Toshihiko Sato

Masahito Takahashi

Satoru Haga

Teruaki Kisu

Teruo Kisu, Legal Representative

Haruko Kisu, Legal Representative

Julian Darryn White

Kiyoo Ito

Teruo Kisu

Haruko Kisu

To realize a small size and high detection accuracy in a substance detection apparatus. A charge detection field effect transistor and a control circuit therefor are provided in each cell, and the control circuit controls the charge detection field effect transistor so that the drain-source voltage and the drain current of the charge detection field effect transistor are always maintained constant. The control circuit may be formed in a CMOS configuration including a small number of elements in a small area using a standard CMOS integrated circuit technique.

Material detector

A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film () constituting the channel forming region from an n type poly-crystalline silicon film () constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film (); and reducing an effective impurity concentration in the poly-crystalline silicon film ().

Longitudinal MISFET manufacturing method, longitudinal MISFET, semiconductor storage device manufacturing method, and semiconductor storage device

A controllable conduction device in the form of a transistor comprises source and drain regionsbetween which extends a conduction path P for charge carriers, a gatefor controlling charge carrier flow along the conduction path and a multiple layer structureproviding a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Controllable conduction device with electrostatic barrier

A semiconductor integrated circuit device including a plurality of memory cells, each having a storage MOSFET holding information in a gate of the storage MOSFET, a write transistor supplying a write information voltage corresponding to the information to the gate storage MOSFET, and a capacitor having first and second terminals. Word lines and data lines are coupled with the memory cells. The first capacitor terminal is coupled with one of the word lines and the second capacitor terminal is coupled with the gate of the storage MOSFET. In a read operation of the semiconductor integrated circuit device, the gate voltage of the storage MOSFET is boosted by a transition of the word line from a first voltage to a second voltage greater than the first voltage.

Semiconductor integrated circuit device

A vertical MIS is provided immediately above a trench-type capacitor provided in a memory cell forming region of a semiconductor substrate, and a lateral nMIS is provided in the peripheral circuit forming region of the semiconductor substrate. After forming the capacitor, the lateral nMIS is formed. In addition, after forming the lateral nMIS, the vertical MIS is formed. Furthermore, after forming a capacitor, an isolation part of the peripheral circuit is formed.

Method of manufacturing semiconductor device having a plurality of trench-type data storage capacitors

Semiconductor integrated circuit device with improved storage MOSFET arrangement

Method of manufacturing semiconductor device and semiconductor device

Semiconductor memory device and manufacturing method

Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n type semiconductor regions via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.

Method of manufacturing semiconductor memory device and semiconductor memory device

A semiconductor integrated circuit device utilizing a memory cell containing a transistor to write information and a storage MOSFET to retain an information voltage in the gate, a word line placed to intersect with a write data line and a read data line, for connecting to the control terminal of the write transistor and a memory cell array for issuing an output on the read data line corresponding to the read signal from said memory cell in response to a select signal from said write transistor and by means of a data select circuit select one from among said plurality of read data lines from the data line select circuit and connect to either a first or second common data line, precharge said read data line to a first voltage within a first period, discharge said read data line to a second voltage by means of a second storage MOSFET of said memory cell set to on status for said word line selected within the second period, precharge said first and second common data lines to a third voltage between said first and said second voltages within said first period and, amplify the read signal appearing on either of the common data lines from the read data line selected by said data line select circuit within said second period by using the precharge voltage on said other common data line as a reference voltage.

A memory device includes a memory node ( ) to which charge is written through a tunnel barrier configuration ( ) from a control electrode ( ). The stored charge effects the conductivity of a source/drain path ( ) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers ( ) of polysilicon of 3 nm thickness and layers ( ) of Si N of 1 nm thickness, overlying polycrystalline layer of silicon ( ) which forms the memory node. Alternative barrier configurations ( ) are described, including a Schottky barrier configuration, and conductive nanometer scale conductive islands ( ), which act as the memory node, distributed in an electrically insulating matrix.

Memory device

Semiconductor memory device and manufacturing method thereof

A flash memory cell is based on a floating gate transistor design in which a floating gate is separated from a channel by a tunnel oxide. The cell is programmed and erased by electrons tunnelling on and off the floating gate through the tunnel oxide. To retain charge stored on the floating gate, the tunnel oxide is relatively thick. As a result it takes a long time, of the order of 100 &mgr;s, to program and erase the cell, Injection of charge onto the floating gate is helped by hot-electron and channel inversion effects. However, no such effects help tunnelling of charge off the floating gate, Introduction of a silicon heterostructure hot-electron diode comprising an intrinsic silicon region promotes electron transport from the floating gate during erasing cycles and so reduces the erase voltage. Furthermore, the intrinsic silicon region provides an additional barrier to charge leakage, so permitting a thinner tunnel oxide to be used and thus read/write cycles become shorter.

Memory device using hot charge carrier converters

Semiconductor memory device with MIS transistors

Growing community of inventors

Cambridge, United Kingdom

Kazuo Nakazato