Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Kazuo Nakao

Akira Muramatsu

Ikuo Yoshihara

Teruo Tanaka

Shigeo Nagashima

Tadashi Hirose

Kousuke Sakoda

Takehisa Hayashi

Naoki Hamanaka

Makoto Nohmi

Keiko Shinada

Kuniaki Matsumoto

Koichi Haruna

Tsutomu Tashiro

Tamotsu Nishiyama

Youichi Takeuchi

Nobuyuki Saida

Yoichi Takeuchi

In a parallel computer including L=n.sub.1 .times.n.sub.2 .times. - - - .times.n.sub.N processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L.times.(1/n.sub.1 +1/n.sub.2 + - - - +1/n.sub.N) crossbar switches in total comprises N dimensional lattice coordinates (i.sub.1, i.sub.2, - - - , i.sub.N), 0.ltoreq.i.sub.1 .ltoreq.n.sub.1 -1, 0.ltoreq.i.sub.2 .ltoreq.n.sub.2 -1; - - - , 0.ltoreq.i.sub.N ; and .ltoreq.n.sub.N -1 given to each processor element as the processor element number, crossbar switches for decoding a dimensional field in a processor element number having specific position and length depending upon the number of lattice points of a particular dimension and for performing the switching operation with regard to the dimension, interconnection of n.sub.k processor elements having processor element numbers, which are different only in the k-th dimensional coordinate for arbitrary k, i.e., having processor element numbers ##EQU1## by using one of the crossbar switches, each of the crossbar switches having n.sub.k inputs and n.sub.k outputs, and the interconnection performed with respect to all (L/n.sub.k sets) of coordinates (i.sub.1, i.sub.2, - - - , i.sub.k-1, i.sub.k+1, - - - , i.sub.N) of N-1 dimensional subspace excluding the k-th dimension, the interconnection being further performed for all values of k (1.ltoreq.k.ltoreq.N).

Interconnection network and crossbar switch for the same

In a parallel computer including L=n.sub.1 x n.sub.2 x - - - x n.sub.N processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L x (1/n.sub.1 +1/n.sub.2 +- - - +1/n.sub.N) crossbar switches in total comprises N dimensional lattice coordinates (i.sub.1, i.sub.2, - - - , i.sub.N) , 0.ltoreq.i.sub.1 .ltoreq.n.sub.1-1, 0.ltoreq.i.sub.2 .ltoreq.n.sub.2-1, - - - , 0.ltoreq.i.sub.n .ltoreq.n.sub.N-1 given to each processor element as the processor element number, crossbar switches for decoding a dimensional field in a processor element number having specific position and length depending upon the number of lattice points of a particular dimension and for performing the switching operation with regard to the dimension, interconnection of n.sub.k processor elements having processor element numbers, which are different only in the k-th dimensional coordinate for arbitrary k, i.e., having processor element numbers ##EQU1## by using one of the crossbar switches, each of the crossbar switches having n.sub.k inputs and n.sub.k outputs, and the interconnection performed with respect to all (L/n.sub.k sets) of coordinates

A parallel computer has an operation request function and a plurality of processor elements. Each processor element has a sharable distributed memory for holding data, and is interconnected to a network to permit communication. Each processor element comprises a request sent unit for sending an operation request message for causing another processor element connected to a memory module to execute a recursive defining operation. The memory module stores data to be recursively defined. Each processor element further comprises an operation request execution element for accepting a message from another processor, temporarily stopping any other operation of the processor element in accordance with the content of the message, and executing the requested operation. Registers are also used for executing the operation requested by the other processor in addition to the general purpose registers and floating point registers.

Method and apparatus for executing an operation request signal in a

A plurality of elemental processors each include a local memory for storing data and task programs and an execution section for executing the task programs. A communications section transfers data among the processors. In a method of parallel processing with these elemental processors, a task program is executed in one of the processors. A detection operation is conducted to determine whether the data from the task program is to be copied to the local memories of other processors. The detection is based on predetermined information which is stored in the local memory of the processor which performs the task program and indicates which of the other processors will need the data. The detection also determines which of the other processors that will require access to the data are ready to receive the data. Concurrently and in parallel with the execution of the task program, the data is transmitted to each of the elemental processors that are awaiting the data with only a write instruction and without any communications instruction.

Method of parallel processing for avoiding competition control problems

In accessing a memory, each element processor executes a program constructed so as to designate an address belonging to a predetermined local address area for each element processor. When a memory write instruction is executed by an element processor, it is detected if the memory address designated by the instruction coincides with a predetermined address. If detected, a predetermined address belonging to a local address space of another element processor and assigned to the first-mentioned predetermined address, and the data written in response to the write instruction, are sent to the other element processor to instruct the data to be written therein as a copy data. A next task to be executed is decided independently for each element processor.

Parallel computer with distributed shared memories and distributed task

A sequence of calling clauses and all clauses in a procedure that includes the selected clauses are displayed simultaneously, and the present point of execution is displayed being overlapped on the above displays. In particular, the program source list of a procedure being processed is displayed, and the latest execution statuses of the executed terms are graphically displayed around the terms on the displayed program source list.

Method of displaying execution trace in a logic programming language

In order to improve the efficiency of test and debug procedure based on delarative program understanding of a program described by a logical language, the operation which has been executed for each procedure is grasped. On the basis of information relating to the grasped operation, the operation range of each procedure is expressed clearly by making thick only sides which have actually operated among four sides of a box-shaped figure surrounding each head term and end body term of each clause included in each procedure.

Method for displaying operation range of logical language

In order to highly speed up the pattern matching of tree structured data in a logic programming language, the priority order is set when the data owned by the individual nodes of a tree structure are to be transversely sought, and the tree structured data are expressed in a vector type, in which they are arranged in that priority order, so that they are compared consecutively from the head for each element of the vector.

Pattern matching method for tree structured data

A reliability analyzing system for manufacturing processes is disclosed, which comprises a computer system provided with a data memory device, a central processing device and input/output devices, terminals which input/output information into/from said computer system, and output devices for manufacturing sites; whereby said data memory device stores required specifications for each product, works for manufacturing and controlling processes, information relating to items, such as required specifications, works, control items, etc. and information mutually relating different items, and on the basis of the stored information, reliability analysis for each process is effected for all the processes and reliability analysis for each required specification is performed for all the required specifications.

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Sagamihara, Japan

Kazuo Nakao