Sanyo Electric Co., Ltd.

Kazuo Naganawa

Yoshikazu Asano

Yoshihiro Hori

Yoshihito Higashitsutsumi

Toshihiro Furusawa

Kazuo Ishimoto

Yosuke Mizutani

Shuji Yanase

A first digital processor (13) generates luminance data Y and color difference data U, V, using image data D1. The processor (13) further generates separated luminance data Y1, Y2 by halving the luminance data Y, and generates a compound color difference data C by combining the color difference data U, V for output. An JPEG encoder 13 compresses the separated luminance data Y1, Y2 and the compound color difference data C to generate compressed luminance data y1, y2 and compressed color difference data c. A modulator 15 modulates the compressed luminance data y1, y2 and the compressed color difference data c to generate luminance modulated signals m1, m2 and color difference modulated signal mc. A recording/reproducing section 16 records the luminance modulated signals m1, m2 and the color difference modulated signal mc in parallel onto the first to third recording tracks of a magnetic tape (20).

Image signal recording and reproducing apparatus

A MUSE sound decoder detects a broadcasting/non-broadcasting identification flag included in the control signals in an applied MUSE signal to determine whether the MUSE signal is broadcasted or non-broadcasted. The MUSE sound decoder further includes a frame synchronization protection circuit for protecting frame synchronization over a predetermined frame synchronization protection time period when the frame synchronization pattern is not detected at the proper timing. The frame synchronization protection circuit sets the frame synchronization protection time period to a long time period when the MUSE signal is determined to be a broadcasted MUSE signal, and to a short time period when the MUSE signal is determined to be a non-broadcasted MUSE signal. Appropriate muting of a sound signal can be carried out according to the condition of the received MUSE signal.

Broadcast/non-broadcast MUSE signal sound decoder with a variable

A frame synchronizing signal detecting circuit detects a frame synchronizing signal in a video signal. When the frame synchronizing signal is not detected by the frame synchronizing signal detecting circuit, a clamp level switching circuit is responsive to a switching signal from a timer circuit for generating alternately an upper clamp potential V.sub.+ and a lower clamp potential V.sub.-. When the frame synchronizing signal is detected by the frame synchronizing signal detecting circuit, the clamp level switching circuit generates a normal clamp potential V.sub.0. A clamping pulse generating circuit is responsive to an output from the frame synchronizing signal detecting circuit for generating a clamping pulse. A clamping circuit is responsive to the clamping pulse for clamping an analogue video signal at the clamp potentials V.sub.0, V.sub.+ or V.sub.- from the clamp level switching circuit.

Clamping circuit for clamping video signal

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Kakamigahara, Japan

Kazuo Naganawa