Fujitsu Corporation

Kazuo Nagahori

Hisamitsu Tanihira

Renri Nakano

A casing in which a module substrate is to be enclosed, the casing includes a rail portion that slidably supports the module substrate, and a shutter portion provided so as to open and close an opening for ventilation. The casing includes a pin portion that is provided in the rail portion and contacts an edge of the module substrate while the module substrate is supported by the rail portion. The casing includes a link mechanism that allows the shutter portion to move in accordance with the moving distance of the pin portion.

Casing, module substrate, and air-cooling system

An appratus and a method for controlling initialization of a processor system having a memory device which reads data based on a memory request signal and outputs the read data to a data bus and having a processor which outputs the memory request signal based on a reset signal, to read an initialization program stored in the memory device. A detector detects the memory request signal output by the processor. A counter counts the memory request signals detected by the detector. A selector which has predetermined data provided, selects the data in accordance with the counting by the counter and outputs the selected data to the data bus as the initiation information.

Apparatus and method for controlling initialization of a processor system

Data for designating a status mode is written beforehand in a data portion of a data-type microinstruction. When power is introduced, first, the data type microinstruction is read. Next, a status-mode setting circuit generates an enable signal. The enable signal is only generated at the initial reading of the data-type microinstruction. The status-mode designating data written in the data portion of the microinstruction is stored in a status-mode memory in response to the enable signal. A central processing unit reads the status-mode designating data that has been stored in the status-mode memory and executes processing conforming to the status mode read.

Method and apparatus for setting the status mode of a central processing

A data shifting circuit comprises a barrel shifter for shifting by a plurality of bits data having a width twice that of a certain data width, and a data controller for supplying the same data having the certain data width commonly to the most significant bits and the least significant bits of the barrel shifter means.

Data shifting circuit capable of an original data width rotation and a

In a system for testing an instruction queue circuit connected to an external memory via a bus controller provided in a processor having a microprogram control unit, an operation unit connected to the microprogram control unit and connected, via an internal bus, to the instruction queue circuit, the instruction queue circuit-including a plurality of queue buffers, a writing unit writes internal bus information transferred via the internal bus into the instruction queue circuit in response to a first instruction generated by the microprogram control unit. The internal bus information is contained in the first instruction. A reading unit reads the internal bus information from the instruction queue circuit in response to a second instruction generated by the microprogram control unit. A gate circuit outputs the internal bus information to the internal bus in response to a third instruction generated by the microprogram control circuit. The internal bus information is used to test the instruction queue circuit.

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Kawasaki, Japan

Kazuo Nagahori