Fujitsu Corporation

Mori, Hiromi

Takebayashi, Tomoyoshi

Yamamoto, Kaoru

Miyazaki, Tsuyoshi

Murano, Kazuo

Kazuo Murano

Tetsuo Soejima

Toshitaka Tsuda

Toshiaki Watanabe

Norio Murakami

Shigeo Amemiya

Kazuo Yamaguchi

Takao Moriya

Yutaka Awata

Hiroaki Komine

Takafumi Chujo

Shigeyuki Unagami

Fumio Amano

Kazuo Iguchi

Tomoyoshi Takebayashi

Tomohiro Shinomiya

Misao Fukuda

Syunji Fujikawa

Motohide Takahashi

Yoshikazu Itoh

Tatsuki Hayashi

Hiromi Mori

Tsuyoshi Miyazaki

Kaoru Yamamoto

Kazuo Iquchi

A programmable multiplexing/demultiplexing system used in a digital communication network, suitable for an ISDN to be developed. The system including a phase adjusting unit, a bit length varying unit, a start timing control unit, and a processor which variably controls the three units. The phase adjusting unit variably controls the phase of an internal clock in accordance with received data, and the thus-adjusted clock is used by the remaining two units. The bit length varying unit variably controls the bit length of the received data. The start timing control variably controls the start timing of each transmission and reception processing carried out alternately by the processor.

Programmable multiplexing/demultiplexing system

Disclosed is a frame synchronizing apparatus in a receiving equipment for receiving digital signals for PCM communication. The digital signals consists serial signals at a rate of f.sub.0 (bps). The serial signals include a frame synchronizing signal consituting n bits or a part of the frame synchronizing signal, collectively arranged in one frame. To attain a high-speed operation and a shorter synchronization establishing time, the apparatus comprises a latching circuit for converting the serial signals into parallel signals and for latching the parallel signals, and a circuit for detecting a plural number of times of synchronization during the n bit interval in one frame.

Frame synchronizing apparatus

A multiplexing apparatus of a bit interleave type for time-division multiplex on PCM signals of a plurality of channels bit by bit to convert the PCM signals into a high-speed PCM signal. To maintain the advantage of the synchronous multiplex system, the multiplexing apparatus has a BSI-code processing function and a bit interleave function and comprises: a BSI-code adding circuit for adding BSI codes to the PCM signals before multiplexing; a BSI-code position shifting means circuit for shifting the positions of the BSI codes in the PCM signals to different positions respectively with respect to the PCM signals of a plurality of channels; and a multiplexing circuit for multiplexing the outputs of the BSI-code position shifting circuit by a bit-interleave mode.

Multiplexing apparatus having BSI-code processing and bit interleave

An adaptive differential pulse code modulation system includes an adaptive quantizer and an adaptive predictor which have a coding characteristic optimized to a voice signal, and a quantizer and a predictor which have a coding characteristic optimized to a voice band MODEM signal. This system is normally used as a coding system optimized to the voice signal, and when this system detects a MODEM training signal, it becomes a coding system optimized to the MODEM signal.

Adaptive differential pulse code modulation system

A digital transmission system comprising at least two transmitting-receiving (T/R) units and a single transmission line connected therebetween. One of the T/R units the first transmits a control signal to the other T/R units with which frame synchronization and timing recovery are carried out using the transmitted control signal. At the same time, the other T/R unit inhibits transmission of send signal therefrom to the first T/R unit. Further, the send signal from one T/R unit to the other T/R unit is transmitted in the form of a frame. Each frame includes, at its end portion, a non-signal duration portion.

Digital transmission system

An information communication system having a plurality of terminal equipment units, a network termination unit, a receive (R) line, and transmit (T) line. The terminal equipment units are commonly connected to the R and T line so as to communicate with the network termination unit. The communication is achieved in the form of successive frame signals, each composed of at least successive channels. Each terminal equipment determines a delay time for channel insertion into the frame signal on the T line. the delay time is determined during a learning identification algorithm operation which takes the transmission delay time along the R and T lines into consideration.

Method and apparatus for adjusting channel insertion timing

A device for discriminating between two values of a signal using DC offset compensation including an automatic gain control circuit, a peak detector circuit and a feedback path from the peak detector circuit to the input circuit of the automatic gain control circuit. The value of the feedback current is regulated so that the maximum value of one of the same polarity signals and the opposite polarity signal coincides with the minimum value of the other of the two signals.

Device for discriminating between two values of a signal with DC offset

An asynchronous transmission system for binary-coded information is disclosed. According to this system, in a transmitting terminal (A), when successive data of the same code in a set of asynchronous data lasts for a predetermined period of time (T.sub.1), a refresh pulse, the polarity of which is opposite to that of the successive data, is added to a transmission signal. However, the addition of such a refresh pulse to the transmission signal is inhibited for a predetermined period of time (T.sub.2) to allow for a change of data. In a receiving terminal (B), a pulse, the width of which is larger or equal to a minimum period of data, and a pulse, the width of which is smaller than or equal to a pulse-width (T.sub.0) of a refresh pulse, can be discriminated and removed by a pulse-width discrimination circuit. As a result, the refresh pulse is not present in the output signal of the pulse-width discrimination circuit. Thus, the original asynchronous data is restored.

Asynchronous transmission system for binary-coded information

A timing-phase recovery circuit, which is suitably mounted on a digital LSI, includes a timing phase recovery circuit. The timing-phase recovery circuit includes a first circuit for extracting a digital timing signal from a received input analogue signal, a second circuit for detecting a virtual zero crossing included in the digital timing signal in synchronism with a sampling signal and a third circuit for carrying out a phase shift with respect to the sampling signal in order to tune the timing signal to the frequency of the virtual zero crossings in a very short period of time.

Timing-phase recovery circuit

The present invention disclosed an adaptive delta modulation system which examines the several preceding bits of an output of the adaptive delta modulation, and discretely changes a quantizing stepsize of said output so as to compand the same. According to the present invention the system detects the several preceding bits of the output of the adaptive delta modulation, changes the stepsize of that output, counts the output bits of the adaptive delta modulation from the time when stepsize changes, regardless of whether the output is '0' or '1', and changes said stepsize when the counted value reaches a value which is predetermined in accordance with the quantizing stepsize at that time thereby correcting the mistracking which is generated in an adaptation logic circuit between a coder terminal and decoder terminal.

Adaptive delta modulation system for correcting mistracking

The system according to the present invention carries out two way communication of a digital signal between a master terminal having its own clock source and a slave terminal, which is synchronized with the clock of the master terminal. The master terminal sends a digital signal originating from its own clock to the slave terminal and the slave terminal in turn sends a digital signal based on a clock signal which is derived from the received digital pulse from the master terminal.

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Tokyo, Japan

Kazuo Murano