Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Vlsi Engineering Corporation

Kazuo Mihashi

Hiromi Tsukada

Yutaka Kobayashi

Kazumasa Yanagisawa

Goro Kitsukawa

Hitoshi Miwa

Atsushi Nozoe

Masayuki Nakamura

Tetsurou Matsumoto

Shoji Wada

Tetsu Udagawa

Yoshitaka Kinoshita

Kyoko Ishii

Tatsuyuki Ohta

Yoshiaki Ouchi

Mitsuhiro Takano

Sinichi Miyatake

Shouji Wada

Nobuo Komatsu

A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

Dynamic Random Access Type Semiconductor Device

Testing method for a semiconductor memory device

A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as curent signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

Bi-CMOS semiconductor memory device, including improved layout structure

A dynamic type RAM is provided wherein the level of a precharge control signal supplied to a gate of a precharge MOSFET to precharge complementary data lines to a half level is made the half level during a period from the memory access until the selection of the word line, at the latest. Also, the precharge control signal, corresponding to a memory mat selected according to establishing of an address, is set to a low level, while the precharge control signal corresponding to a non-selective memory mat is set to a high level.

Semiconductor memory device having means for providing a precharge

Growing community of inventors

Sakaiminato, Japan

Kazuo Mihashi