Kabushiki Kaisha Toshiba

Kazuo Konishi

Koji Maruyama

Toshiaki Sato

Shimpei Yoshioka

Meisei Nishikawa

Tomoyuki Maekawa

Hideyuki Naka

Toshihiro Morohoshi

Tsuyoshi Hagiwara

Masafumi Umeda

Kazuhiro Takashima

Naoki Akamatsu

Takato Katagiri

Setsuo Terasaki

Takaaki Suyama

Tomiyoshi Fukumoto

Masao Iwasaki

Hiroaki Matsubara

Kazuyuki Ooishi

Kohichi Satoh

A control system realizes a playback function by playing back stream data read out from a medium by using a decoder. When special playback functions corresponding to pause, fast forward, and rewind are to be performed, the control system moves a read start pointer to the head of a data block constructing a data format, and sets as a restart position of a playback operation.

Digital recording/playback apparatus

A letterbox image detection apparatus for detecting a letterbox image by detecting a boundary of an image area and a non-image area, so as to display the image area on a full screen according to the detection result but not to display the non-image area. The apparatus includes timing pulse generator for generating a timing pulse for splitting one screen image into N columns (N is an integer of 2 or more), image property calculator for calculating the image property of the N horizontal sections (hereinafter referred to as columns) split by the timing pulse generator, inter-line difference calculator for calculating the inter-line difference of the N image properties, edge detector for comparing the inter-line difference with a predetermined upper first threshold th,and for detecting the edge, and edge position data holder for holding the vertical position data of the in-column edge detected by the edge determinator.

Letterbox image detection apparatus

This invention provides a memory card device using an EEPROM as a semiconductor memory. When a data write-in defective area is detected in the storage area of the EEPROM, a space area is retrieved from the storage area of the EEPROM as a relieving area and data to be written into the data write-in defective area is written into the relieving area. Then, when the relieving area becomes full and a data write-in defective area is detected in the storage area of the EEPROM, another space area is retrieved from the storage area of the EEPROM as a new relieving area and data to be written into the data write-in defective area is written into the new relieving area.

EEPROM memory card device having defect relieving means

A memory card apparatus has an EEPROM as a semiconductor memory. Each time data is written in the EEPROM, link data representing a recording location of the data is written and managed in a link table. The link table has a flag region with a flag which is set when data write in the EEPROM is requested and is reset when the link data has completely been written in the link table. In case of card removal during operation or power failure, the flag set in the flag region of the link table is not reset and remains. Thus, by checking the flag area of the link table, the occurrence of card removal during operation or power failure can be detected, and various countermeasures can be conducted. Thus, the correspondency between the recorded contents in the EEPROM and the contents in the link table can be maintained as much as possible.

Memory card apparatus including a link table for managing the

A time-base conversion system including a first clock generator for generating a read clock based on a reference signal, a second clock generator for generating a write clock by dividing the read clock, a memory, a circuit for writing video data in the memory based on the write clock, a circuit for reading the video data recorded in the memory based on the read clock, and a time-base compressor for determining a compression ratio of the video data time-base by determining a division ratio of the write clock.

Time-base conversion system

A memory card apparatus using EEPROMs as semiconductor memories. Externally input data are temporarily recorded in a buffer memory and are subsequently written in the EEPROMs. Verify processing is automatically performed between the buffer memory and the EEPROMs. Similarly, data read out from the EEPROMs are temporarily recorded in the buffer memory and are subsequently output to an external unit. Even with the EEPROMs, it seems that this memory card can be used in the same manner as a memory card using an SRAM, when viewed from the outside of the card.

Memory card apparatus using EEPROMS for storing data and an interface

Memory card device

In a variable length code demodulating apparatus, a bit length of the variable length code is examined to determine if it is longer than a specified bit length. The most significant bits equal in number to the specified bit length is selected from variable length codes which have a bit length exceeding the specified bit length. The most significant bits of the variable length code are converted to a conversion code which replaces the most significant lists. The conversion code has a bit length less than the specified bit length. An addressing to a conversion table in which each fixed length code is stored corresponding to each variable length code is performed on the basis of the least significant lists and the conversion code substituting for the most significant lists.

Variable length code demodulating apparatus and address control method

A digital peak noise reduction circuit for reducing peak noise of an input digital signal having variable levels corresponding to a predetermined sound volume range. The circuit includes a division circuit for dividing the level of the input signal; a ROM for supplying a plurality of data expansion rates, each expansion rate being defined by a relationship between a different specific range of input digital signal level and the predetermined range; a multiplier for multiplying the digital audio data with the reciprocal related data output from the ROM; a multi-stage shift circuit for supplying a plurality of data compression rates, (each compression rate correspond to the expansion rates of the ROM) and for producing an output signal having a level corresponding to the selected compression rate; a de-emphasis circuit for compensating for specified frequency characteristics of the output signal; and a feedback circuit for supplying the output signal to the division circuit for controlling the ROM.

Digital peak noise reduction circuit

A delta-sigma modulation analog to digital converter for converting an analog input signal to a digital output signal. The converter includes a clock generator for generating a very high frequency clock signal, a dither signal generator responsive to the clock signal generator for generating a dither signal which is synchronized with the clock signal, an adder coupled to the dither signal generator for combining the analog input signal and the dither signal, a delta-sigma modulation type quantizer coupled to the adder for quantizing the analog input signal and the dither signal in response to the clock signal and a data decimation circuit responsive to the clock signal and coupled to the delta-sigma modulation type quantizer for decimation prescribed quantization data from the quantized signal and producing a digital signal corresponding to the analog input signal.

Delta-sigma modulation analog to digital converter

A convolution arithmetic circuit has a multiplier/accumulator to multiply two digital data sequences and add up the products. The sequences are stored in memories which cycle at the same rates and with different scales. One memory containing the multiplicand data is periodically updated, while the other memory containing coefficient data has a storage capacity of about twice the previous memory.

Convolution arithmetic circuit for digital signal processing

A convolution arithmetic circuit has an accumulator to multiply two digital data sequences and add up the products. The sequences are stored in memories which cycle at the same rates and with different scales, the memory containing the multiplicand data being periodically updated.

Growing community of inventors

Yokohama, Japan

Kazuo Konishi