Hitachi, Ltd.

Renasas Technology Corporation

Kazuo Koide

Toshiro Takahashi

Mikio Yamagishi

Masaaki Ohkawa

Akira Yamagiwa

Nobuo Yoshida

Noboru Masuda

Tetsuo Nakano

Masao Mizukami

Kazunori Nakajima

Bunichi Fujita

Toshihiro Okabe

Kazuhisa Suzuki

Seiichi Kawashima

Kazumichi Yamamoto

Toyohito Ikeya

Satoshi Hososaka

Junya Kudoh

Kazutaka Mori

A method is provided for manufacturing an integrated circuit device having a plurality of wiring layers including a first wiring layer which is not the upper most layer among the plurality of wiring layers and a second wiring layer higher than the first wiring layer in the plurality of wiring layers. An interlayer dielectric film is provided to cover the first wiring layer. Holes are then formed in the interlayer dielectric film and a mask film is formed to cover some of the holes. Etching using the mask film is then carried out and an insulating film formed on the interlayer dielectric film is removed, including the bottoms and/or insides of the holes. The mask film is then removed and a conductive member is formed inside the holes.

Method of manufacturing a semiconductor integrated circuit device having a plurality of wiring layers and mask-pattern generation method

When signal transmission is performed between two semiconductor integrated circuit devices in synchronization with a clock signal using a small signal amplitude relative to an operating voltage of the two semiconductor integrated circuit devices, a received signal is held in the receiving semiconductor integrated circuit device in synchronization with the clock signal while the small signal amplitude of the held signal is kept substantially without change. The received signal having the small signal amplitude is amplified along a signal transmission path including a combined logic circuit to a subsequent latch circuit of the receiving semiconductor integrated circuit device.

Semiconductor integrated circuit device and low-amplitude signal receiving method

Semiconductor integrated circuit device and low-amplitude signal

A variable delay circuit including delay devices each having a plurality of delay units connected successively, only some of the delay units of the delay devices being connected to a signal transmission line, wherein a delay time is controlled by activating or inactivating the plurality of delay units according to control signals applied to control input terminals provided respectively for said plurality of delay units. A clock signal supply device for supplying a second clock signal to a logic circuit block, said clock signal supply device having a clock signal generator for generating a first clock signal and a reference signal and a phase adjusting means for adjusting the phase of the first clock signal phased on a phase difference between the first clock signal and the reference signal and outputting the phase-adjusted signal as a second clock signal, wherein the phase adjusting unit comprises a first variable delay circuit capable of delay operation in initial adjustment of the first clock signal, a second variable delay circuit, disposed in series with the first variable delay circuit, for performing the delay operation after the initial adjustment, and control circuits for controlling delay times of the first and second variable delay circuits.

Variable delay circuit and clock signal supply unit using the same

One paired wiring traveling in parallel to a transmission path of a signal and a transmission path of reference voltage is used, and a terminal end resistor matched with the characteristic impedance is installed, and in a receiving circuit connected thereto, a differential input circuit with offset set to about 1/2 of the terminal end voltage is used, and an output circuit of open drain is used in a transmitting circuit. A high-speed information processing section using such a bus circuit and a low-speed information processing section using a conventional low-speed bus are mutually connected through an interface circuit to construct the system hierarchically.

Signal transmission method, signal transmission circuit and information

A CMOS LSI stably operates with high speed ECL LSI's to provide a data processing system. Two power sources of a negative ECL operation voltage and a positive CMOS operation voltage are provided. In a CMOS LSI, input signals of ECL level are successively amplified through an ECL input interface having a p-channel differential amplifier and an n-channel type differential amplifier, fed to the CMOS output buffer circuit and converted to the CMOS level, processed in a CMOS internal circuit, and output at the ECL level through output open-drain MOSFETs. The CMOS LSI is operated by two power sources which are level-shifted in correspondence with the ECL signal amplitude, instead of using ground potential and a positive voltage such as VDD.

CMOS integrated circuit device and data processing system using the same

Data to be processed are transferred by connecting a one-way element having a reduced parasitic capacitance such as the Schottky diode between an output MOSFET having an open drain structure and an output terminal to be connected with a bus line terminated by an impedance element.

Semiconductor integrated circuit device and data processing system

A semiconductor integrated circuit device includes an interface corresponding to a relatively high signal level; an interface corresponding to a relatively low signal level; and an internal circuit made responsive to a signal through either interface for generating a signal to be transmitted to the other interface. The interface corresponding to a relatively high level, the internal circuit, and a drive control circuit constituting the input circuit and output circuit of the interface corresponding to a relatively low level are operated by an operating voltage corresponding to the relatively high level. An output element of the output circuit in the interface corresponding to a relatively low level, which is to be driven by the drive control circuit, is operated by an operating voltage corresponding to the relatively low level.

Semiconductor integrated circuit device capable of outputting a

Because a bypass circuit BP connected in parallel with serial paths of first and second storage circuits MF and SF has less serially-connected stages of gates incorporated therein than the storage circuits and has shorter information transfer delay of input data to an output terminal 21 than the storage circuits, the bypass circuit BP outputs the information to the output terminal before the outputs of the storage circuits are determined when data supplied to a data input terminal 20 is fetched synchronously with a clock signal CK. The first and second storage circuits MF and SF are master/slave-operated in diagnosis mode, and the output operation of the bypass circuit BP is inhibited according to the states of signals C1 and C2 for controlling their master/slave operations regardless of the clock change of the first control signal CK. Thus, the master/slave operations of the first and second storage circuits MF and SF are assured in the diagnosis mode.

Circuit having a master-and-slave and a by-pass

Herein disclosed is a semiconductor integrated circuit device, in which a buffer circuit having a MISFET of a second conduction type and arranged in a first region of the principal plane of a semiconductor substrate of a first conduction type is supplied with a first supply voltage and in which an internal circuit having a complementary MISFET and arranged in a second region of the principal plane of the semiconductor substrate different from the first region is supplied with a second supply voltage independent of the first supply voltage at least over the semiconductor substrate and having a potential equal to that of the first supply voltage. The MISFET of the buffer circuit is formed in the principal plane of a well region of a first conduction type formed in the principal plane of the semiconductor substrate. Between the well region of the first conduction type and the semiconductor substrate, there is formed a separating region for separating the two electrically.

Semiconductor integrated circuit device

A flip-flop circuit includes a data input terminal, a data output terminal, a memory circuit and a bypass circuit having a shorter delay time than that of the memory circuit. The memory circuit and the bypass circuit are connected in parallel between the data input terminal and the data output terminal so that the data are outputted to the data output terminal through the bypass circuit when the data are written in the memory circuit. As a result, the delay time of the flip-flop circuit is shortened.

In a gate array including a plurality of output buffer circuits whose output levels change simultaneously with one another, a power source voltage or a reference voltage is supplied to the plurality of output buffer circuits whose output levels change simultaneously with one another by the same and exclusive power source voltage wiring or reference voltage wiring and is separated from power source voltage wirings or reference voltage wirings connected to other output buffer circuits and this wiring design is made by DA (Design Automation) combining fixed patterns with connection patterns. This designing method can prevent any adverse influences of the operations of the output buffer circuits whose output levels change simultaneously with one another on the other output buffer circuits and on input buffer circuits.

Semiconductor integrated circuit device and wiring method thereof

In order to reduce undesirable output noise, an output circuit is provided which includes a first output MOSFET which is interposed between an output terminal and a first power source voltage, and a second output MOSFET which is interposed between the output terminal and a second power source voltage. In particular, in accordance with one aspect of the invention, a feedback circuit is interposed between the output terminal and the gate of the first output MOSFET or/and between the output terminal and the gate of the second output MOSFET to negatively feedback voltage to provide a gentle level change for the output voltage. In other embodiments, a short-circuit arrangement is provided which is interposed between the gate and source of the first output MOSFET or/and between the gate and source of the second output MOSFET. The short-circuit arrangement is temporarily held in a transferring state at the initial stage of a process in which the corresponding first or second output MOSFET is turned on to provide the desired gentle level change.

Output circuit

A complex logic circuit which fulfills the requirements of high-speed operation, low power consumption and simplicity in circuit setup, includes a first ECL (emitter coupled logic) circuit and a second ECL circuit. The first ECL circuit which drives relatively light loads does not have an emitter follower output circuit in the output thereof. The second ECL circuit which drives relatively heavy loads has an emitter follower output circuit in the output thereof. A level shift means is connected between the load resistor of the first ECL circuit and a point of operation potential, and the voltage drop across the level shift means is set to be substantially equal to the voltage across the base and emitter of the emitter follower output transistor of the second ECL circuit. Thus, the signal levels of the first and second ECL circuits can be made to coincide.

Growing community of inventors

Iruma, Japan

Kazuo Koide