Seiko Epson Corporation

Kazuo Kobayashi

Hidehiko Yajima

A driver IC, which is mounted on an active matrix substrate by means of COG, is provided. The driver IC includes an input-output circuit, an internal circuit region having a plurality of internal circuits, a plurality of substrate-coupling bumps coupled to the input-output circuit, and at least one dummy bump. The dummy bump is placed facing opposite to one of the plurality of internal circuits which becomes an object of light shielding.

Bumped IC, display device and electronic device using the same

A display driver capable of operating in any one of multiple gradient display modes drives a liquid crystal panel in which the first L common electrodes are simultaneously selected in a first selection period and successive groups of L common electrodes are simultaneously selected in successive selection periods. 8-bit display data for each segment electrode are simultaneously read from a display data RAM and latched. First and second sub-decoders decode divided upper and lower four bits of the 8-bit display data, respectively. In a first mode, the data is for a four gradient display for each of four pixels on each segment electrode. In a second mode, the data is for a two gradient display for each of eight pixels on each segment electrode.

Display driver apparatus, and electro-optical device and electronic equipment using the same

The present invention provides a pulse width modulation signal generation circuit that generates pulse width modulation signals that can suppress the increase in power consumption caused by the increase in grayscale, together with a data line drive circuit, electro-optical device, and electronic instrument that use the same. The pulse width modulation signal generation circuit generates a pulse width modulation signal based on (a+b) bits of grayscale data that have been read from RAM. During that time, the circuit detects a match between a first count value and the high-order the a-bit grayscale data and a match between a second count value, which is one less than that first count value, and the high-order the a-bit grayscale data. In a decoder circuit, one of the match detection results is used to output a pulse width modulation signal, in correspondence with a result of decoding a frame number and the low-order b-bit the grayscale data.

Pulse width modulation signal generation circuit, data line drive circuit, electro-optical device, and electronic instrument

The data bits of a first image data unit representing a first range of 0-255 continuous color tones are mapped to a second image data unit having an expanded bit count capable of representing a second range of continuous color tones greater the first range. Of the available colors tones in the second range, 256 color tones are selected and associated with the 256 data combinations achievable with the first image data unit. A decoder is used to convert each data combination in the first image data unit into its corresponding color tone from the second range, which defines its conversion into a second image data unit. In this manner, one can expand the range of displayable colors to approximate the display of true colors associated with a higher resolution without increasing the number of bits of the first image data unit, which is input to a driver IC by an MPU.

Color display method and semiconductor integrated circuit using the same

The invention reduces capacitor coupling between data read bit lines and data write bit lines to thereby prevent error detection of data. A first pair of bit lines BM and {overscore (BM)} that read data from a specified one of memory cells in a memory cell column and a second pair of bit lines BS and {overscore (BS)} that write data in another specified one of the memory cells in the memory cell column are formed in different layers through an interlayer dielectric film. As viewed in a plan view, the space between the first pair of bit lines BM and {overscore (BM)} is wider than the second pair of bit lines BS and {overscore (BS)}, and the second pair of bit lines BS and {overscore (BS)} are disposed between the first pair of bit lines BM and {overscore (BM)}. A first wiring layer that is set a ground potential is disposed in the same layer as the first pair of bit lines BM and {overscore (BM)} and between the first pair of bit lines BM and {overscore (BM)}. Second and third wiring layers that are set at a ground potential are disposed in the same layer as the second pair of bit lines BS and {overscore (BS)} and opposite to the respective bit lines of the first pair of bit lines BM and {overscore (BM)} with the interlayer dielectric film being interposed therebetween.

Growing community of inventors

Suwa, Japan

Kazuo Kobayashi