Tokyo Electron Limited

Tokyo Electron Limi Ted

Kazuo Kibi

Chishio Koshimizu

Naoki Matsumoto

Yohei Yamazawa

Akira Koshiishi

Manabu Iwata

Masaru Sugimoto

Ryuji Ohtani

Kunihiko Hinata

Daisuke Yano

Hidetoshi Hanaoka

Mitsuhiro Okada

Masashi Saito

Noriyuki Kobayashi

Manabu Sato

Hiroki Yamazaki

Toshihiro Hayami

Yoshinobu Ohya

Yoshinobu Ooya

Kenji Suzuki

Akihiro Takahashi

Wataru Sakamoto

Shigetsugu Fujita

A method of manufacturing a semiconductor device includes: planarizing a surface of a substrate having a conductive material embedded in a first hole so as to expose the conductive material embedded in the first hole, wherein the first hole is formed in a region which is on an insulating film laminated on the substrate and is surrounded by a spacer film; laminating a mask film on the surface of the substrate; forming a second hole in the mask film such that at least a portion of an upper surface of the conductive material embedded in the first hole is exposed; embedding the conductive material in the second hole; and removing the mask film.

Method of manufacturing semiconductor device

There is formed, on a stack formed by alternately stacking an oxide film and a nitride film or an oxide film and a polysilicon film on a substrate, a hard mask in which two or more kinds of lines made of mutually different materials are arranged in order. Then, a photoresist is applied onto the hard mask. Furthermore, the photoresist is trimmed until one line is exposed from the end of the hard mask. Moreover, one line of the hard mask exposed beneath the photoresist is etched. Furthermore, a part of the stack exposed beneath the hard mask is etched. The etching of the photoresist, the hard mask, and the stack is repeated while changing etching conditions.

Method for manufacturing three-dimensional semiconductor memory device

In a method for manufacturing a semiconductor device that comprises a semiconductor fin including a source region and a drain region, which configure a field effect transistor, and a fixed potential line provided in parallel to the semiconductor fin, the method comprises: a first step of preparing an intermediate body in which an insulating layer is provided on the source region (P-type conductive region), the drain region (N-type conductive region), and the fixed potential line; and a second step of simultaneously forming contact holes leading to the source region, the drain region, and the fixed potential line, in the insulating layer.

Method of simultaneously forming contacts to a power rail and the source and drain regions of a FinFET

A plasma processing method includes executing an etching process that includes supplying an etching gas into a process container in which a target substrate is supported on a second electrode serving as a lower electrode, and applying an RF power for plasma generation and an RF power for ion attraction to turn the etching gas into plasma and to subject the target substrate to etching. The etching process includes applying a negative DC voltage to a first electrode serving as an upper electrode during the etching to increase an absolute value of self-bias on the first electrode. The etching process includes releasing DC electron current generated by the negative DC voltage to ground through plasma and a conductive member disposed as a ring around the first electrode, by using a first state where the conductive member is connected to a ground potential portion.

Plasma processing apparatus and method

A plasma etching apparatus includes an upper electrode and a lower electrode, between which plasma of a process gas is generated to perform plasma etching on a wafer W. The apparatus further comprises a cooling ring disposed around the wafer, a correction ring disposed around the cooling ring, and a variable DC power supply directly connected to the correction ring, the DC voltage being preset to provide the correction ring with a negative bias, relative to ground potential, for attracting ions in the plasma and to increase temperature of the correction ring to compensate for a decrease in temperature of a space near the edge of the target substrate due to the cooling ring.

An apparatus includes an upper electrode and a lower electrode for supporting a wafer disposed opposite each other within a process chamber. A first RF power supply configured to apply a first RF power having a relatively higher frequency, and a second RF power supply configured to apply a second RF power having a relatively lower frequency is connected to the lower electrode. A variable DC power supply is connected to the upper electrode. A process gas is supplied into the process chamber to generate plasma of the process gas so as to perform plasma etching.

A plasma processing apparatus includes a first and second electrodes disposed on upper and lower sides and opposite each other within a process container, a first RF power application unit and a DC power supply both connected to the first electrode, and second and third radio frequency power application units both connected to the second electrode. A conductive member is disposed within the process container and grounded to release through plasma a current caused by a DC voltage applied from the DC power supply. The conductive member is supported by a first shield part around the second electrode and laterally protruding therefrom at a position between the mount face of the second electrode and an exhaust plate for the conductive member to be exposed to the plasma. The conductive member is grounded through a conductive internal body of the first shield part.

An apparatus includes an upper electrode and a lower electrode for supporting a wafer disposed opposite each other within a process chamber. A first RF power supply configured to apply a first RF power having a relatively higher frequency is connected to the upper electrode. A second RF power supply configured to apply a second RF power having a relatively lower frequency is connected to the lower electrode. A variable DC power supply is connected to the upper electrode. A process gas is supplied into the process chamber while any one of application voltage, application current, and application power from the variable DC power supply to the upper electrode is controlled, to generate plasma of the process gas so as to perform plasma etching.

A plasma processing apparatus includes a processing container, an exhaust unit, an exhaust plate, an RF power application unit connected to a second electrode but not connected to the first electrode and configured to apply an RF power with a single frequency, the second electrode being connected to no power supply that applies an RF power other than the RF power with the single frequency, a DC power supply connected to the first electrode but not connected to the second electrode, the first electrode being connected to no power supply that applies an RF power, and a conductive member within the process container grounded to release through plasma a current caused by the DC voltage, the conductive member supported by the first shield part and laterally protruding therefrom only at a position that is located, in a height-wise direction, between a mount face and the exhaust plate and below a bottom of a focus ring.

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Nirasaki, Japan

Kazuo Kibi