Hitachi, Ltd.

Mochida Pharmaceutical Co., Ltd.

Konishiroku Photo Industry Co., Ltd.

Hodogaya Chemical Co., Ltd.

Konica Corporation

Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Renesas Technology Corp.

Nippon Steel Corporation

Ajinomoto Co., Ltd.

Sony Computer Entertainment Inc.

Mitsui Toatsu Chemicals, Incorporated

Hitachi Media Electronics Co., Ltd.

The Kansai Electric Power Co., Inc.

Tokyo Medical and Dental University

Kazuo Kato

Masahiro Iwamura

Kozaburo Kurita

Takao Sasayama

Yoji Nishio

Hideo Sato

Takashi Hotta

Ei Mochida

Takashi Sase

Shigeo Kuboki

Hideo Maejima

Yasuhiro Nakatsuka

Tadaaki Bandoh

Shigeya Tanaka

Sin-ichi Sinoda

Ikuro Masuda

Kimihiro Murakami

Fumio Murabayashi

Hidenori Mochizuki

Kazuji Yamada

Ichiro Yamamoto

Yasuji Kamata

Kenkichi Yamashita

Shoichi Kotoku

Ichitomo Miwa

Jun Okuda

Katsuaki Kato

Kanji Kawakami

Masahiro Watanabe

Hiroki Tokunaga

Akio Uemura

Takeshi Kishido

Akinori Haga

Kenichi Onda

Tetsuya Yoshino

Nobuaki Miyakawa

Satoru Shimba

Ryushi Shimokawa

Yoshikazu Watanabe

Kiyoshi Mizuguchi

Ichiro Ikushima

Tomohiko Douken

Takashi Kageyama

Seiichi Ueda

Masahiro Matsumoto

Hideki Miyazaki

Nobuyasu Kanekawa

Yoshinori Sato

Hiroshi Morita

Fumio Tajima

Akihiko Emori

Toshiyuki Fujii

Kiyoshi Matsubara

Kazuhiro Watanabe

Tsunehiro Endo

Noboru Akiyama

Tohru Kobayashi

Masayuki Miki

Eiichi Ueda

Yasuyuki Kojima

Hirokazu Aoki

Seiko Suzuki

Shinzo Tamai

Masayuki Tani

Shigeki Tsuchitani

Koichi Takeuchi

Takeshi Hirayama

Kenji Kumashiro

Hideki Aoki

Takashi Fujimura

Masaaki Takahashi

Masayoshi Naito

Shigeaki Yoshida

Yoshihiro Yokota

Hiromitsu Araki

Makoto Aihara

Kenji Ito

Hatsuhiko Naitoh

Fumio Hamada

Yasushige Akada

Tomoyuki Someya

Naohiro Toki

Kiyotoshi Yamashita

Ryosaku Kanzawa

Isao Arai

Motofumi Kurahashi

Kikuo Tomita

Kazuyoshi Takizawa

Shizuo Saito

Kozo Iwasaki

Hiroyuki Hanei

Kazumi Nishijima

Kazuyuki Matsuura

Kenji Ogawa

Ichiro Miyagawa

Koji Yamaji

Husayoshi Kakizaki

Kazuhiro Suzuki

Hitoshi Inaba

A semiconductor device capable of executing fault injection test on a plurality of failure detection mechanism in a short time is provided. The semiconductor devicehas a plurality of hierarchical modules and an error control modulefor controlling errors in the plurality of hierarchical modules. Each hierarchical module has a safety mechanism to detect failures in the functions of the components that make up the hierarchical modules. The error control moduleincludes a status registerconfigured to record data indicative of the status of failure of each hierarchical module, and a fault injection functionthat outputs an error signal to the status registerto perform fault injection test. The error signal is inputted into the safety mechanism via the status register

Semiconductor device, semiconductor systems and test-control methods for executing fault injection test on a plurality of failure detection mechanism

For reducing the load on a server as much as possible during transfer of data from the server to a terminal, each terminal is capable of playing out a network game in cooperation with a local network game terminal. To this end, the local network game terminal and one or more other network game terminals are grouped in the local network game terminal. Additionally, group information is generated with which the game servercan recognize the grouped terminals as one user group, and representative terminal information is also generated with which other network game terminals in the same user group can recognize that the local network game terminal is the representative terminal. Bi-directional communications, including transfer of the data received from the game serverand the representative terminal information, are made with other network game terminal(s) in the user group.

Network game terminal, game server, method for handling network games, and recording medium

An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal Kwhich is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal Kand the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.

Information processor and information processing system utilizing interface for synchronizing clock signal

A compound represented by the following Formula (I):(wherein A represents oxygen atom or &#x2014;NR&#x2014; (Rrepresents hydrogen atom or lower alkyl group); Rrepresents nitro group, lower alkoxycarbonyl group, carbamoyl group unsubstituted or mono- or di-substituted by lower alkyl group, unprotected or protected hydroxyl group, unprotected or protected carboxyl group, lower alkyl group substituted by unprotected or protected hydroxyl group, or tetrazolyl group; and Rrepresents hydrogen atom, cyano group or lower alkylsulfonyl group, provided that when A is &#x2014;NR&#x2014;, it is excluded that Rrepresents unprotected or protected hydroxyl group or lower alkyl group substituted by unprotected or protected hydroxyl group) or its salt, and method for producing the compound, and a pharmaceutical composition containing the compound as active ingredient.

4-hydroxypiperidine derivatives having analgesic activity

A phase locked loop (PLL) circuit is provided to operate in a broad band, including two separate loops one of which is for feed-back of an output from an oscillator to the same oscillator through its associative proportional control unit and the other of which is for feed-back of an output of an oscillator to the same oscillator via an integral control unit. The proportional control unit is arranged to control an output frequency of the oscillator and is operable to generate a control signal based on a difference between input and output signals. The integral control unit is arranged to control the phase of an output signal of the oscillator to thereby generate a control signal based on a phase difference between input and output signals.

Phase-locked loop circuit, information processing apparatus, and information processing system

A measuring circuit capable of performing a high-accuracy measurement by eliminating inductive influence from an ambient noise voltage source. An electric circuit including a signal circuit of high impedance, a wiring conductor and a meter is provided with a shielding resistance member having a significantly lower resistance than that of the signal circuit in dependence on an inter-terminal voltage of the high impedance signal circuit and a shield formed of an electrically conductive material disposed in association with the wiring conductor. A voltage distribution function of the shielding resistance member is matched equally to that of an inter-terminal voltage distribution function of the signal circuit. By measuring a line voltage through the medium of the high impedance signal circuit shielded by the shielding resistor, high accuracy measurement can be realized without undergoing adverse influences of parasitic capacitance and induction.

Electric circuit shielding

The measuring precision of an electric power measuring apparatus is improved. A voltage measuring apparatus for sheathed power cable is disclosed as including; a first conductive member arranged to contact the sheathing material for sheathing a power cable conductor, a second conductive member for forming a capacitance between the ground and itself, current voltage converting operation for converting a current signal flowing between the first conductive member and the second conductive member into a voltage signal having a waveform proportional to the current signal, and a voltage value calculating operation for calculating the voltage value applied to the power cable from the signal converted by the current voltage converting operation.

Voltage measuring apparatus for sheathed power cable

An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K , And the operation timing of an interface provided between at least one pair oflogic devices is synchronously controlled by the clock signal K .

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

A power supply apparatus is disclosed comprising a voltage detection circuit connected to a smoothing circuit and an AC switch having a low ON-resistance with no offset voltage at current-buildup. The AC switch is further connected to a secondary winding of a current transformer. When an output voltage of the smoothing circuit increases up to a predetermined value, the output voltage is detected by the voltage detection circuit and the AC switch is turned on by an output signal of the voltage detection circuit, whereby the secondary winding of the current transformer is short-circuited.

Power supply apparatus comprising a voltage detection circuit and method for using same

A waveform shaping circuit is provided so that the duty factor of clock pulses can be set to 50% with high accuracy even if the clock pulses are of a low voltage and a high frequency. An inverter which receives the clock pulses through an alternating current coupling capacitor is provided with a non-linear limiter element for limiting an amplitude of an output symmetrically on positive and negative sides thereof. A first current-limiting impedance and a second current-limiting impedance are connected between a power supply side terminal of the inverter and a power supply bus and between a grounding side terminal of the inverter and a grounding bus, respectively.

Waveform shaping device

The signal x to be transmitted is converted to the redundant code f(x) by the redundancy coder and transmitted via the isolating capacitor of the isolator . When the signal f(x) redundancy-coded and transmitted is the coded word f(xi), the decoder outputs xi which is inferred as an equivalent original signal and when an error occurs and the signal f(x) does not match the coded word f(xi), the decoder corrects the error and outputs xi which is inferred as an original signal.

Signal transmission apparatus using an isolator, modem, and information processor

In a CMOS gate array, each of bonding pads corresponding to input cells for signals and bonding pads corresponding to input cells for supply voltages is formed of a plurality of conductor layers, whereas each of bonding pads (non-connected pads) corresponding to input/output cells not to be used is formed of, for example, the uppermost conductor layer. Thus, the bonding pad (non-connected pad) corresponding to the input/output cell not to be used becomes greater in the thickness of an underlying insulator film and longer in its spacing from a semiconductor substrate in comparison with each of the bonding pad for the signal and the bonding pad for the supply voltage.

Semiconductor integrated circuit device

An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

Information processor and information processing system utilizing clock

An electric apparatus has a plurality of electric parts and a casing made of electrically conductive material for accommodating therein or mounting thereon a plurality of electric parts. The casing, which has a cavity therein, is provided with a plurality of projections for radiating heat generated by the electric parts in the cavity. The casing is provided with openings for allowing a heat conductive medium to flow into and out of the casing. Further, an electric apparatus has a plurality of electric parts and a casing made of electrically conductive material for accommodating therein or mounting thereon a plurality of electric parts. The casing is provided with openings for allowing a heat conductive medium to flow into and out of the casing. The casing is provided therein with a partition wall which is made of electrically conductive material for dividing the interior of the casing into a plurality of zones along a direction of a flow of the heat conductive medium.

Electric apparatus having heat radiating fin

Growing community of inventors

Tohkai, Japan

Kazuo Kato