Sanyo Electric Co., Ltd.

Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Kazuo Itoh

Hironori Akamatsu

Hiroyuki Yamauchi

Yoshinobu Yamagami

Satoshi Ishikura

Katsuji Satomi

Hiroyuki Nishino

Teruhito Takeda

Shojiro Kido

Masahiro Makino

Hiromichi Goto

Toshiyuki Kudo

Hirohisa Ohtsuki

Toshiyuki Hirata

Mitsuru Tanabe

Kazunori Kidera

Shigeaki Yamasaki

Shinichi Iwasaki

Mariko Kifuji

Mikio Sahashi

Akihiko Matsuya

Motoi Okada

Osamu Kanbara

Masafumi Kitamura

Mahito Tsuji

A visible light communication apparatus includes: an on/off switch connected in series to a load circuit including a light emitting diode; an impedance circuit connected in series to the on/off switch; a feedback circuit that feeds back an error between a voltage drop across the impedance circuit and a reference voltage potential to a voltage source as a feedback signal; a drive circuit that turns on and off the on/off switch in accordance with a communication signal which is a binary signal; an isolation circuit that transmits power while being electrically isolated; and an auxiliary power supply circuit that is connected between two output terminals of the voltage source, generates an auxiliary supply voltage, and supplies power based on the auxiliary supply voltage generated to the on/off switch and the drive circuit via the isolation circuit.

Visible light communication apparatus

A controller switches between modes each having a different connection state of a DC power supply and the capacitor with respect to first and second output points by controlling switches. A generation unit generates a reference wave including at least one carrier wave. The modes are classified into a sustaining mode in which no current is caused to flow to the capacitor, a charging mode in which a current is caused to flow to the capacitor, and a discharging mode in which a current in a direction opposite to that in the charging mode is caused to flow to the capacitor. The controller switches between the sustaining mode and a charging or discharging mode according to the comparison result between a signal wave and the reference wave.

Power converting device, and power conditioner using same

An illumination light communication apparatus includes: a light source which emits illumination light; a power supply circuit for supplying constant current to the light source; a switch which is connected in series to the light source, and intermittently interrupts current which flows through the light source; a signal generating circuit which generates a binary communication signal which controls on and off of the switch to modulate the illumination light; and a current limiting circuit which is connected in series to the light source and the switch, and limits the current which flows through the light source to prevent the current from exceeding a current set value which is variable.

Illumination light communication apparatus and communication module

A semiconductor device having a multilayer interconnect structure allowing heat in an interconnect layer at an intermediate level to be effectively dissipated is provided. A lower-layer interconnect (), an intermediate interconnect (), an upper-layer interconnect (), a first contact via () formed to electrically connect the lower-layer interconnect () to the intermediate interconnect (), and a second contact via () formed to electrically connect the intermediate interconnect () to the upper-layer interconnect () are provided. When viewed from above, the first and second contact vias () both have a rectangular shape with their long sides extending in the same direction, and overlap with each other.

Semiconductor device comprising multilayer interconnect structure with overlapping vias

A grid interconnection devicecomprises a receiver configured to receive an adjustment instruction and a controller configured to control a backward flow power on the basis of the adjustment instruction. The adjustment instruction includes group information indicating an application group to which the adjustment instruction is applied among a plurality of groups G. Customers(each includes a power supply device) are grouped depending on the distance from a substation.

Grid interconnection device and power control system

A grid interconnection devicefor interconnecting a power storage device to a power distribution system to which alternating current power is distributed, the grid interconnection device comprises a receiverand a controller. The receiverreceives a second adjustment instruction transmitted before a first adjustment instruction. The controllercontrols the power storage amount on the basis of the second adjustment instruction.

Grid interconnection device, grid interconnection system, and power control system

A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistorsandincluded in a latch section is different from at least one of a potential supplied to a word lineand a potential supplied to bit linesand; a latch potential control circuitfor switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin; and a read/write control circuitfor controlling the potential supplied to the sources of the load transistorsandto be lower than at least one of the potential supplied to the word lineand the potential supplied to the bit linesand, during an arbitrary period of at least a read operation in the test mode.

Semiconductor memory device

A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistorsandincluded in a latch section is different from at least one of a potential supplied to a word lineand a potential supplied to bit linesanda latch potential control circuitfor switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pinand a read/write control circuitfor controlling the potential supplied to the sources of the load transistorsandto be lower than at least one of the potential supplied to the word lineand the potential supplied to the bit linesandduring an arbitrary period of at least a read operation in the test mode.

A starter of single-phase induction motor having main winding and auxiliary winding energized by alternating current power source, including a casing, a positive characteristic thermistor connected in series to the auxiliary winding, an auxiliary positive characteristic thermistor connected parallel to the positive characteristic thermistor, a bimetal, and an enclosed compartment accommodated in the casing for enclosing the snap action bimetal and auxiliary positive characteristic thermistor.

Starting device for single-phase induction motor

A technology for achieving energy saving by efficiently controlling each of a plurality of equipment systems is proposed. The equipment control system includes an air conditioner system, a refrigerator system, a refrigerator/freezer showcase system and a central coordinator. Status data related to electric equipment provided in the systems is transmitted to the central coordinator. The central coordinator computes control data for the systems, based on the status data of the electric equipment transmitted. The central coordinator is provided with the function of computing the control data, based only on the status data of the corresponding electric equipment and the function of computing the control data, allowing for the status data of another of electric equipment in addition to the status data of the corresponding electric equipment.

Equipment control system

A static random access memory (SRAM) includes a memory array, a sense amplifier circuit, a replica circuit and a dummy cell. The replica circuit has the same elements as memory cells, and includes plural replica cells which output a signal whose level corresponds to the number of stages provided to a common replica bit line. The dummy cell is connected as a load with the common replica bit line. The source of a drive transistor of the dummy cell is connected with a power source which is at the High level. This suppresses a leak current flowing from a replica bit line to the dummy cell.

Static random access memory (SRAM) with replica cells and a dummy cell

A dummy cell includes two series-connected OFF-state transistors, one end of the series circuit which is formed by these two transistors is connected with a constant voltage source, and the other end of the series circuit is connected with a replica bit line. This suppresses a leak current flowing from the replica bit line to the dummy cell and therefore gives optimal start-up timing to a sense amplifier circuit.

Semiconductor memory device and circuit layout of dummy cell

An SRAM device according to the present invention comprises a memory cell including a first pair of bit lines connected to a first port, a second pair of bit lines connected to a second port, a first inverter, and a second inverter having an input terminal connected to the output terminal of the first inverter and an output terminal connected to the input terminal of the first inverter. The memory cell has a first region in which an impurity of a first conductivity type is diffused and second and third regions each of a second conductivity type which are adjacent to the first region and opposed to each other with the first region interposed therebetween. The first pair of bit lines are disposed on the second region and the second pair of bit lines are disposed on the third region.

SRAM device using MIS transistors

The accuracy in forming a gate electrode or an interconnect is improved by using a dummy gate electrode or a dummy interconnect. In addition, the dummy gate electrode or the dummy interconnect is removed, so that a region where the dummy gate electrode or the dummy interconnect has been disposed can be used as a region for forming another composing element.

Method for fabricating semiconductor device

A keel-tipped stylus has a constricted terminal portion which is mounted on narrow shoulders which is in turn mounted on wide shoulders. The keel-tipped stylus is formed from a V-shaped stylus which engages into a spiral groove formed in an abrasive lapping disc. As the lapping disc rotates, the V-shaped stylus runs along the groove to lap the constricted terminal portion together with the narrow and wide shoulders.

Growing community of inventors

Osaka, Japan

Kazuo Itoh