Fujitsu Corporation

Kazuo Itabashi

Taiji Ema

Osamu Tsuboi

Koichi Hashimoto

Kenichi Inoue

Wataru Futo

Yuji Yokoyama

Shinichiroh Ikemasu

Junichi Mitani

Seiichi Suzuki

Itsuo Yanagita

Kazuhiro Mizutani

A method of manufacturing a semiconductor device on a semiconductor substrate having a first region and a second region. This method beings by forming a transistor in the first region of said semiconductor substrate. This transistor includes a pair of impurity diffusion regions and a gate electrode. Then forming a first insulating film over the first and second regions with this first insulating film covering the transistor in the first region. Thereafter, patterning the first insulating film to selectively remove the first insulating film in the second region. Then forming a second insulating film over the first and second regions. Thereafter, forming at least one contact hole through the second and first insulating film. The contact hole reaches one of the impurity diffusion regions. Finally, forming a conductive layer in the contact hole.

Method of manufacturing a semiconductor device with self-aligned contacts

A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating films, and electrically connected to the conductive plug through the second aperture.

Semiconductor device with self-aligned contact and its manufacture

The semiconductor device comprises a semiconductor substrate,of a first conduction-type, first wells,of a second conduction-type formed in a first region on the primary surface of the semiconductor substrate,, a second well,formed in a second region on the primary surface of the semiconductor substrate,other than the first region, a third well,of the first conduction-type formed in the first well, and high-concentration impurity-doped layers,of the first conduction-type formed in deep portions of the semiconductor substrate spaced from the primary surface of the semiconductor device in device regions. In the semiconductor device having triple wells according to the present invention, the high-concentration impurity-doped layers are formed in deep portions inside of the device regions. Accordingly, in the case where the wells have a low concentration so that the transistors have a low threshold voltage, the deep portions of the wells can independently have a high concentration. As a result, punch-through between the source/drain diffused layer of the transistor formed in the well in the well (double wells), and the well outside of the double wells can be prevented. This structure is also effective to prevent latch-up.

Semiconductor device and method for fabricating semiconductor device

A semiconductor device including a semiconductor substrate 10 of a first conduction-type, first wells 20a, 20b of a second conduction-type formed in a first region on the primary surface of the semiconductor substrate 10, a second well 22a formed in a second region on the primary surface of the semiconductor substrate 10 other than the first region, a third well 22b of the first conduction-type formed in the first well, and high-concentration impurity-doped layers 26 of the first conduction-type formed in deep portions of the semiconductor substrate spaced from the primary surface of the semiconductor device in device regions. In a semiconductor device having triple wells, the high-concentration impurity-doped layers are formed in deep portions inside of the device regions. Accordingly, in the case where the wells have a low concentration so that the transistors have a low threshold voltage, the deep portions of the wells can independently have a high concentration. As a result, punch-through between the source/drain diffused layer of the transistor formed in an inner well of a double well, and the well outside of the double well can be prevented. This structure is also effective to prevent latch-up.

Semiconductor device having triple wells

The method for fabricating a semiconductor device comprising the steps of: forming a first oxide film 12 on a surface of a semiconductor substrate 10 and forming a first nitride film 14 on a surface of the first oxide film 12, the first nitride film 14 having a predetermined pattern; isotropically etching the first oxide film 12, with the first nitride film 14 as a mask, to partially expose the surface of the semiconductor substrate 10 and form a hollow 16 just under an end portion of the first nitride film 14; forming a second oxide film 18, thinner than the first oxide film 12, at least on the surface of the semiconductor substrate 10 exposed at the outside of the first nitride film 14 and on a inner surface of the hollow 16; depositing a second silicon nitride film 20 on at least the second oxide film 18, the second silicon nitride film 20 being more liable to oxidation than the first silicon nitride film 14; and oxidizing a region where the first silicon nitride film 14 is absent, with the first silicon nitride film 14 as a mask, to form a device isolation film 24. The second silicon nitride film 20 is formed of a silicon nitride film which is more liable to oxidation, so that when the device isolation film 24 is formed by oxidizing away the second silicon nitride film 20, thickness disuniformity can be decreased.

Method for fabricating isolation region for a semiconductor device

A semiconductor memory device includes a semiconductor substrate, and a memory cell formed on the semiconductor substrate and including two transfer transistors, two driver transistors and two thin film transistor loads. The thin film transistor load includes a first gate electrode, a first insulator layer formed on the first gate electrode, a semiconductor layer formed on the first insulator layer, a second insulator layer formed on the semiconductor layer, and a shield electrode formed on the second insulator layer. This shield electrode shields the thin film transistor.

Semiconductor memory device having thin film transistor and method of

An SRAM semiconductor device having a parallel connection of two series circuits each having a driver transistor and a load connected in series, a wiring for connecting an interconnection point between the driver transistor and load of each of the two series circuits to a control terminal of the driver transistor of the other of the two series circuits, and a transfer transistor connected to each interconnection point, wherein the driver transistor and transfer transistor each are an insulating gate field effect transistor having a channel region formed on the surface of a semiconductor substrate at a predetermined area, source/drain regions on both sides of the channel region, and an insulated gate above the channel region, and the transfer transistor has a resistor region having an impurity concentration lower than the source/drain regions on both sides of the channel region of the driver transistor, the resistor region being contiguous to the channel region of the transfer transistor.

SRAM semiconductor device

A thin film transistor (TFT) load type static random access memory (SRAM) which includes a memory capacitor in addition to the stray capacitance. The SRAM includes a semiconductor substrate and a memory cell provided on the semiconductor substrate. The memory cell includes first and second transfer transistors, first and second driver transistors, first and second thin film transistor loads and first and second memory capacitors. The first and second memory capacitors include a storage electrode, a dielectric layer which covers the storage electrode, and an opposing electrode formed on the dielectric layer. A connection region is provided in which the storage electrode of the first memory capacitor, the drain region of the second thin film transistor load and the gate electrode of the first driver transistor are connected.

A method of producing a semiconductor memory cell. The memory cell includes two transfer transistors, two driver transistors, two thin film transistor loads and two word lines respectively coupled to gate electrodes of the transfer transistors. The method includes (a) forming a field insulator layer on a semiconductor substrate, (b) forming a gate insulator layer, (c) forming a gate electrode of a driver transistor by forming and patterning a first conductor layer, (d) forming a first insulator layer on the first conductor layer after impurity regions are formed in the semiconductor substrate, (e) forming and patterning a second conductor layer on the first insulator layer, (f) forming a second insulator layer on the second conductor layer, (g) forming and patterning a third conductor layer on the second insulator layer, (h) forming a third insulator layer on the third conductor layer, (i) forming a contact hole which extends from the top surface of the third insulator layer to the top surface of the first conductor layer, the contact hole extending through the second conductor layer and the third conductor layer, and (j) forming a fourth conductor layer which extends into the contact hole to make contact with the first conductor layer, the second conductor layer and the third conductor layer.

Method of producing static random access memory device having thin film

A method of producing a memory cell on a semiconductor substrate. The memory cell includes two transfer transistors, two driver transistors, two thin film transistor loads, and two memory capacitors. A field insulator layer is formed on the semiconductor substrate. A gate insulator layer is formed above the field insulator layer. A gate electrode of a driver transistor is produced by forming a first conductor layer above the gate insulator layer. Impurity regions are formed in the semiconductor substrate using the field insulator layer and the first conductor layer as masks. A first insulator layer is then formed. Source, drain and channel regions of a thin film transistor load are produced by forming a second conductor layer and injecting impurities into the second conductor layer. A second insulator layer is formed above the second conductor layer. A contact hole is formed to extend from the second insulator layer, through the second conductor layer, and to the first conductor layer. A storage electrode of a memory capacitor is produced by forming a third conductor layer which makes contact with the first conductor layer and the second conductor layer through the contact hole. A dielectric layer covering the storage electrode of the memory capacitor and a fourth conductor layer forming an opposing electrode of the memory capacitor are then successively produced.

Method of producing a semiconductor memory device having thin film

A semiconductor memory device includes a semiconductor substrate, a memory cell formed on the semiconductor substrate and including first and second transfer transistors, first and second driver transistors and first and second thin film transistor loads, and first and second word lines extending generally parallel to each other along a predetermined direction and respectively coupled to gate electrodes of the first and second transfer transistors. Each of the first and second thin film transistor loads include first and second impurity regions which sandwich a channel region formed by a semiconductor layer provided on the semiconductor substrate, and a gate electrode formed by confronting conductor layers and isolated from the channel region. The first driver transistor includes a drain which is coupled to one of the impurity regions of the first thin film transistor load and to a gate of the second driver transistor via a first connection region, and the second driver transistor includes a drain which is coupled to one of the impurity regions of the second thin film transistor load and to a gate of the first driver transistor via a second connection region. The first and second connection regions are independently provided and have the same structure.

Static random access memory device having thin film transistor loads

A semiconductor memory device includes a semiconductor substrate, a memory cell provided on the semiconductor substrate and including first and second transfer transistors, first and second driver transistors and first and second thin film transistor loads, where each of the first and second transfer transistors, the first and second driver transistors and the first and second thin film transistor loads have a source, a drain and a gate electrode, and a connecting region in which the drain of the second thin film transistor load, the gate electrode of the first thin film transistor load and the gate electrode of the first driver transistor are connected. The gate electrode of the first driver transistor, the gate electrode of the first thin film transistor load and the drain of the second thin film transistor load are made of conductor layers which are stacked on the semiconductor substrate with an insulator layer interposed between the conductor layers, and a top one of the stacked conductor layers makes contact with a top surface of a bottom one of the stacked conductor layers and with side surfaces of each conductor layer provided between the top and bottom conductor layers within the connecting region.

Semiconductor static RAM having thin film transistor gate connection

Semiconductor devices and methods for producing semiconductor devices to be produced by conducting a combination of a step for producing a gate elctrode of a first conductor layer which is piled on a gate insulator, a step for producing a drain region which is connected with an n.sup.+ -region located under the gate electrode by employing the gate electrode as a part of the mask, and a step for piling, on or over the gate electrode, a second conductor layer connected with the n.sup.+ -region through a contact hole produced in the gate electrode.

Growing community of inventors

Kawasaki, Japan

Kazuo Itabashi