Fujitsu Corporation

Nippon Telegraph and Telephone Corporation

Nec Corporation

Kazuo Iguchi

Tetsuo Soejima

Shigeo Amemiya

Tomohiro Shinomiya

Koji Tezuka

Hiroshi Takeo

Toshiaki Watanabe

Hiroaki Komine

Shinji Ohta

Naoaki Yamanaka

Motoo Nishihara

Hiroshi Nakamura

Haruo Yamashita

Hiromi Ueda

Michio Kusayanagi

Kazuo Murano

Misao Fukuda

Takatoshi Kurano

Youichi Sato

Ikuo Tokizawa

Naomasa Hanano

Multiple access system for communication network

A cross-point type switch includes a plurality of basic elements arranged in rows and columns so as to form a matrix arrangement of the basic elements. Each of the basic elements includes a plurality of input ports, output ports, expanded input ports and expanded output ports. A write/read part is connected to a common memory and has the function of writing data into the common memory and reading out the data from the common memory. A selector part selectively outputs either the data read out from the common memory or data from the expanded input ports to the output ports. The expanded output ports are directly connected to the input ports.

Cross-point type switch using common memories

A usage parameter control circuit for effecting a policing control in an ATM transmission network, comprising a time interval measuring unit for measuring a time interval between a current arrival time of a cell to be judged, and an arrival time of a cell which arrived a reference threshold number of cells before the currently arriving cell arrives; and a judging unit for judging whether or not the measured time interval is shorter than a reference threshold time interval, whereby a longer accessing time is allowed and the circuit construction has a flexible expandability.

Usage parameter control circuit for effecting policing control in an ATM

In a cross-connect apparatus for use in selectively connecting a plurality of input transmission paths to a plurality of output transmission paths, each of the input and the output transmission paths is divided into first through m-th groups each of which is composed of first through n-th transmission paths, first through m-th elementary switch modules are located between the input and the output transmission paths, n in number, of the first through the m-th groups and are connected to a connection switch module through first to m-th input internal path groups each of which is composed of n internal paths and which are extended into first through m-th switch units each of which has input terminals, n(m-1) in number, and output terminals, n in number, where n and m are natural numbers. An i-th one of the switch units in the connection switch module is connected to the input path groups, (m-1) in number, except an i-th internal path group, where i is a natural number between unity and m, both inclusive. The output terminals of the i-th switch unit is connected to an i-th one of the elementary switch modules through an i-th one of output internal paths. This structure serves to avoid an unnecessary detour route in the cross-connect apparatus.

Cross-connect apparatus capable of avoiding a superfluous detour route

Inter-network connecting system

A communication system containing a master station and a plurality of slave stations. The master station receives a request from one of the plurality of slave stations and memorizes one or more requests from one or more slave stations. The master station also sends a request sending allowance signal which addresses one of the plurality of slave stations to give an allowance to send a request for sending data, and sends a data sending allowance signal which addresses one of the plurality of slave stations to give an allowance to send data, according to a request which is memorized. Each of the slave stations detects a request sending allowance signal which addresses its own slave station, and a data sending allowance signal which addresses its own slave station. Each of the slave stations also sends a request for sending data to the master station when its own slave station detects a request sending allowance signal which addresses its own slave station. In addition, each slave station sends data to the master station when its own slave station detects a data sending allowance signal which addresses its own slave station.

Communication system carrying out polling for request and data

A communication system including a master station, a plurality of slave stations each for communicating with the master station, a two-way transmission line connecting the master station and the plurality of slave stations. Each of the slave stations sends a request for further communication with the master station, to the master station when its own slave station is allowed to communicate with the master station and its own slave station has the above request. The master station detects the request for further communication with the master station in a signal sent from a slave station, and memorizes the slave station from which the request for further communication with the master station is detected, until an allowance signal is sent to the slave station from the master station corresponding to the memorizing of the slave station. The master station has a cyclic address pointer which points to an address of a next one of the slave stations in a cyclic order when no slave station is memorized in the master station. The master station outputs the allowance signal to communicate with the master station to a slave station which is memorized in the master station or to a slave station the address of which is pointed to by the cyclic address pointer when no request is memorized in the master station.

Polling communication system with priority control

A coded transmission system wherein each bit of transmitted data having a logical value is coded depending on a coded result of a preceding bit. The coded transmission system contains a sender-side apparatus, a transmission line, and a receiver-side apparatus. In the sender-side apparatus, a resetting bit and a message are generated; a code of a bit last transmitted which is necessary to code a bit which is to be transmitted next is memorized in a first preceding code memorizing circuit; and the content of the first preceding code memorizing circuit is reset to an initial code responding to the resetting bit. A coding circuit receives the resetting bit and the message, codes each bit of the message in accordance with a predetermined coding rule and the content of the first preceding code memorizing circuit, and codes the resetting bit to a predetermined resetting code which is different from the codes used in the coding of the message. In the receiver-side apparatus, a code of a bit last received which is necessary to decode a code of a bit which is received next is memorized in a second preceding code memorizing circuit. A resetting circuit resets a content of a second preceding code memorizing circuit to a predetermined initial code when receiving the resetting code. A decoding circuit decodes the received codes corresponding to the message in accordance with the predetermined coding rule and the content of the second preceding code memorizing circuit.

Coded transmission system with initializing code

A frame synchronization method in which a synchronization detection of a frame synchronization signal using one of n-multiplexed frame synchronization signals derived from a sequence of frame synchronization signals each delayed by one bit from the preceding frame synchronization signal, a synchronization confirmation as synchronization guard by detecting a repetition of the synchronization detections of the frame synchronization signal, a confirmation of the subsequent frame identification signal based on the synchronization confirmation; and a separation of the received multiplexed signals into a plurality of channels based on the synchronization confirmed frame synchronization signal and the confirmed frame identification signal are carried out.

Method and apparatus for frame synchronization

A circuit which operates at the fixed timing and discriminates the control signal is provided and the timing pulse for demultiplexing is controlled in accordance with the discriminated control signal in the receiving part of the synchronized multiplexing system in which the basic signals are generated by inserting the control signal required for multiplexing on the frame structure of basic signal rate and the high level multiplexing signal is formed by multiplexing such basic signals, thereby stable correspondence between the channel at the time of multiplexing in the sending side and the channel after the demultiplexing in the receiving side can be ensured.

Demultiplexing device of synchronous multiplexing system

In a sequential polling type communication network system including a master station, a first channel, a second channel, and at least two slave stations, the master station includes request registration units for registering data transmission requests from slave stations during a data transmission by another slave station, and an interrupt polling unit for polling the slave station which has issued the data transmission request after completion of the data transmission or completion of a polling of a slave station, and the slave station includes a unit for responding to a polling during the data transmission, and transitting a data transmission request when data to be transmitted exists, and for responding to the interrupt polling from the master station, and transmitting the data to the master station until the data transmission is completed.

Polling network communication system having transmission request

A demultiplexing circuit includes a frame synchronization circuit which simultaneously detects the occurrence of a predetermined frame synchronization pattern and the occurrence of a predetermined identification byte within the frame synchronization pattern. Since the pattern and identification bit are detected simultaneously and from the same data, the circuit is simplified and the demultiplexing is performed more quickly and efficiently.

Demultiplexer system

Disclosed is a frame synchronizing apparatus in a receiving equipment for receiving digital signals for PCM communication. The digital signals consists serial signals at a rate of f.sub.0 (bps). The serial signals include a frame synchronizing signal consituting n bits or a part of the frame synchronizing signal, collectively arranged in one frame. To attain a high-speed operation and a shorter synchronization establishing time, the apparatus comprises a latching circuit for converting the serial signals into parallel signals and for latching the parallel signals, and a circuit for detecting a plural number of times of synchronization during the n bit interval in one frame.

Frame synchronizing apparatus

An optical bus type communication system comprises a bus type transmission line consisting of an optical fiber, a light source provided at the one end of the bus type transmission line for sending an optical signal having a constant level to the bus type transmission line, a plurality of optical switches mounted on the bus type transmission line, and a plurality of terminal interfaces. Each terminal interface sends data by switching the corresponding optical switch so that the optical signals on the transmission line are modulated with the data.

Optical bus communication system utilizing frame format signals

In an optical communication system, wherein light intensity modulation with no carrier is performed using a light emitting diode with linear relation of the drive signal current vs. optical output power over a range which changes with frequency of the drive signal, the input signal is modulated for relatively larger amplification of frequencies higher than a predetermined frequency, above the thermal response frequency of the light emitting diode, than for frequencies lower than the predetermined frequency.

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Yokohama, Japan

Kazuo Iguchi