Fujitsu Corporation

Socionext Inc.

Kazuo Horio

Yi Ge

Kazuhiro Yoshimura

Hiroshi Hatano

An arithmetic processing device includes: an arithmetic unit configured to execute an arithmetic operation; and a stream engine configured to execute stream processing, wherein a data bus of the arithmetic unit and a data bus of the stream engine are tightly coupled with each other.

Arithmetic processing device

A product-sum operation circuit that performs a matrix product of a first-matrix and a second-matrix to output a third-matrix, includes; a plurality of multipliers; a plurality of first-adders each of which is configured to add two multiplication results of the plurality of multipliers; a plurality of second-adders each of which is configured to add two addition results of the plurality of the first-adders; an input selector configured to output an element of the first-matrix and an element of the second-matrix to input terminals of the plurality of multipliers according to the number of rows and the number of columns of the first-matrix and the second-matrix; and an output selector configured to select and output the addition results of each of the plurality of first-adders or each of the plurality of second-adders according to the number of rows and the number of columns of the first-matrix and the second-matrix, as the third-matrix.

Product-sum operation circuit and product-sum operation system

A matrix calculation unit may include a matrix operation unit and a converting unit. The matrix operation unit may include functions to perform a matrix operation of a first size with respect to data stored in a memory, and to perform a matrix operation of a second size with respect to the data stored in the memory, where the second size is enlarged from the first size. The converting unit may convert in at least one direction in the memory between a data array suited for the matrix operation of the first size and a data array suited for the matrix operation of the second size.

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Yokohama, Japan

Kazuo Horio