Elpida Memory, Inc.

Kazuo Hidaka

Kayoko Shibata

Akira Ide

Naoki Ogawa

Hideyuki Yoko

Yasuyuki Shigezane

Kenichi Tanamachi

To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal line. The interface chip includes a determination circuit that has a first input terminal connected to the internal wiring through which the current outputted by the first circuit flows and a second input terminal connected to an end of the first internal signal line in the interface chip, and outputs a voltage according to a potential difference between a voltage of the first input terminal and a voltage of the second input terminal.

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Tokyo, Japan

Kazuo Hidaka