Mitsubishi Denki Kabushiki Kaisha

Other

Renesas Technology Corp.

Mitsubishi Electric Semiconductor Software Co., Ltd

Mitsubishi Electric System Lsi Design Corporation

Mitsubishi Electric Semiconductor Software Corporation

Kazuo Asami

Kenichi Takahira

Hisashi Ohno

A power-residue calculating circuit includes: an I/F (interface) circuit with respect to an external bus; an e register holding a key e; a Y register holding a multiplier Y for Montgomery conversion; an N register holding a key N; a B2N register holding a value of (2B+N) calculated during the Montgomery conversion; an X register holding a plaintext X; a calculating circuit performing calculations for encryption and decryption; a P register holding a calculation result P; a power-residue control circuit serving as a state machine when the power-residue calculation is performed; a Montgomery multiplication residue/residue control circuit serving as a state machine when the Montgomery multiplication residue calculation and residue calculation are performed; and an addition/subtraction control circuit controlling calculations addition and subtraction.

Power-residue calculating unit using Montgomery algorithm

In a non-contact IC card, corresponding to increase/decrease of an operation current of an internal circuitry, absorbing current of an ICC fluctuation absorbing circuit is temporarily decreased/increased by the amount corresponding to the increase/decrease, and thereafter, the absorbing current is gradually increased/decreased to the initial value and an output current of a regulator is gradually increased/decreased. Therefore, abrupt change in output current of the regulator can be prevented, and an internal power supply potential can be stabilized.

Semiconductor device with small current consumption having stably operating internal circuitry

A noncontact IC which transmits and receives data to and from a host computer using RF signals has a buffer for storing received data temporarily and a control circuit for controlling operation of the buffer main memory thereof, wherein the control circuit starts processing data stored in the buffer only when no further data is input after a predetermined data receiving time period has elapsed from the latest data input to the buffer.

Noncontact IC card

A sense amplifier circuit comprising a capacitor 12 having a capacity larger than a parasitic capacity 32 of a selected bit line 33, and a differential amplifier 30 for fixing, after the determination of the read data, the voltage level of the selected bit line to a level at which a read current does not flow through said selected bit line, or for cutting a quasi-write in current so as not to be flown into the selected memory cell, thereby the consuming current is reduced and damage of data due to quasi write in is prevented.

Sense amplifier circuit

A microcomputer for an IC card arranged so that only a user mode can be performed after the microcomputer has been shipped to a user. Data representing that the microcomputer has been shipped is written at the time of shipment in a test region of an EEPROM. A shipment confirmation routine for confirming whether the shipment data has been written is performed before execution of a branch routine for branching to other programs in accordance with an executed command supplied from outside the microcomputer. If the shipment data has been written in the test region of the EEPROM as confirmed in the shipment confirmation routine, only branching to the user mode is permitted.

Microcomputer for IC card

An EEPROM apparatus being provided with, in an ECC circuit (6), an ECC code generating unit (19) which automatically generates '5(H)' ((H) represents hexadecimal number), that is, '0101(B)' ((B) represents binary number) as the ECC code when data, in which head is 37 1' and thereafter '0' and '1' are repeated in binary notation, for example, '55(H)', that is, '01010101(B)' is written, as the data to be stored in an EEPROM 50, and automatically generates 'A(H)', that is, '1010(B)' as the ECC code when data, in which head is '0' and thereafter '1' and '0' are repeated in binary notation, for example, 'AA(H)', that is, '10101010(B)' is written, and capable of executing checker pattern test easily and in a short time.

EEPROM apparatus

In a memory unit having a sense amplifier for reading data, the dependence of the memory cell current detection level of the sense amplifier on the power source voltage is restrained. A memory-unit sense amplifier includes a bias circuit (20, 21, 22) for generating an output which mitigates fluctuations in the power source voltage VDD; and a detection result output section (10, 15) which outputs a memory cell current detection result obtained for the purpose of obtaining the value of memory cell data and which has a Pch (P-channel transistor), to the gate of which the output of the bias circuit (20, 21, 22) is connected, whereby fluctuations in the source/gate voltage of the Pch 10 are mitigated so as to restrain the dependence of the memory cell current detection level on the power source voltage.

Memory-unit sense amplifier

An IC card includes a CPU for processing data, a data receiving circuit for receiving data and inputting the data to the CPU, a data transmitting circuit for transmitting data from the CPU, a reset receiving device for receiving an external reset signal, a monitor timer for generating a timer reset signal when there is no response after a prescribed time has elapsed following receipt of data by the data receiving circuit, and a discrimination circuit for determining which of the external reset signal or a timer reset signal from the monitor timer has been received, holding the determination, and resetting the CPU in response to a reset signal.

IC card having a monitor timer and a reset signal discrimination circuit

A non-contact type information card includes a modulating/demodulating circuit, an antenna circuit, a CPU, a RAM, and a clock signal generating circuit. In the non-contact type information card, when the modulating/demodulating circuit receives a new command signal, the CPU determines whether first and second identification information in the new command signal agrees with the first and second identification information in an old command signal. When the first and second identification information of the new command signal agree with that of the old command signal, the CPU stops the operation of the clock generating circuit until the next command signal is received.

Growing community of inventors

Itami, Japan

Kazuo Asami