Mitsubishi Denki Kabushiki Kaisha

Kazunori Saitoh

Koichi Sato

Koji Hirano

A microprocessor, comprising a register 18 for setting either a first mode in which a trap instruction is not executed, or a second mode in which the trap instruction can be executed is set, wherein an instruction decoding circuit 23, in case of operating in the first mode, outputs an internal signal SG1 directing execution of a subroutine call, when decoding a subroutine call instruction, to an instruction executing unit 14, and in case of operating in the second mode, outputs the internal signal SG1 directing execution of a trap when decoding the subroutine call instruction, to the instruction executing unit 14. By such a configuration, a break can be effected in a unit of subroutine under a simple control when debugging the program, and by enabling the breaking without decoding a program to be debugged, the debugging can be effected efficiently under a real time environment.

Growing community of inventors

Itami, Japan

Kazunori Saitoh