Hitachi, Ltd.

Kazunori Onozawa

Atsushi Hiraishi

Hideaki Uchida

Shinji Nakazato

Nobuo Tanba

Nobuyuki Gotoo

Kinya Mitsumoto

Hiroki Miyashita

Yoshikazu Iida

A semiconductor device is constituted by an arrangement of MISFET type SRAM cells structured such that near the edge of active regions of the driver MISFETs in each memory cell, at least one of the source and drain regions of each driver MISFET is offset against the gate electrode of that MISFET. This offset structure is formed by implantation of impurities using a mask covering the edge proximity of the active regions. Moreover, near one edge of the gate electrode of each driver MISFET in an SRAM memory cell, the gate length of that driver MISFET is at least twice the gate length of the MISFET which has the shortest gate length and which constitutes part of a memory cell or a peripheral circuit. Also, at one edge of the gate electrode of each driver MISFET in an SRAM memory cell, the spacing distance between the gate electrode of that driver MISFET and the gate electrode (word line) of a transfer MISFET is made substantially the same in at least two directions. Also, the spacing distance between the gate electrode of each driver MISFET and the gate electrode of a corresponding driver MISFET in an adjacent memory cell is made substantially the same as the spacing distance between the gate electrode of each driver MISFET and the gate electrode (word line) of the transfer MISFET connected thereto.

Semiconductor device having MISFET SRAM cells in which active regions

A semiconductor integrated circuit device is provided which includes a memory cell M, in which a capacitance element C is added to the storage node portion of an inverter circuit composed of a drive MOSFET and a load TFT Qf. The device also includes and a bipolar transistor Tr provided as a peripheral element. A reference power supply line to be connected with the source region of the drive MOSFET Qd and an emitter electrode to be connected with the emitter region of the bipolar transistor Tr are formed of an uppermost thick polycrystal silicon film. Moreover, an intermediate thin polycrystal silicon film between the uppermost polycrystal silicon film and a first polycrystal silicon film (or polycide film) is covered in a memory cell forming region with the uppermost polycrystal silicon film. Still moreover, the uppermost polycrystal silicon film is partially silicified.

Semiconductor integrated circuit device and process for manufacturing

In a semiconductor memory device of the present invention, data read from a memory cell to a pair of complementary data lines or a pair of common data lines are fed directly to an output circuit not through any sense amplifier. As a result, the delay time of the sense amplifier itself is omitted from the address access time of the conventional semiconductor memory device using the sense amplifier, so that the semi-conductor memory device of the present invention can have its address access time made shorter than that of the conventional semiconductor memory device.

Semiconductor memory device

A semiconductor device has, in one embodiment, a p type insulated gate field effect transistor formed in an n type well formed on a semiconductor substrate and an n type insulated gate field effect transistor formed in a p type well formed on the semiconductor substrate. Each of the p type and n type insulated gate-field effect transistors has a composite impurity layer under its gate electrode in a surface portion of its associated well. The composite impurity layer includes a first doped layer of a p type and a second doped layer of an n type adjacent thereto to form a pn junction layer therebetween, while the composite impurity layer includes a first doped layer of a p type and a second doped layer of a p type adjacent thereto to form a junction layer therebetween having a p type impurity concentration lower than that of the p type well.

Method of forming semiconductor device including a CMOS structure having

A semiconductor device facilitates keeping all parasitic resistance values between contact portion of a common source (V.sub.cc) line and intrinsic collector operation regions of respective transistors small enough so as not to exceed predetermined values and so as to be nearly identical. The parasitic resistance values are made small and nearly identical by disposing collector electrode connecting layers between base impurity introducing layers of respective transistors provided with predetermined intervals in a semiconductor substrate. Because of this arrangement to minimize and equalize resistances, the voltage drops generated by the parasitic resistances applied to respective transistors are suppressed so as to be lower than or not substantially exceed the operation threshold voltages of the parasitic transistors.

Semiconductor device

A semiconductor integrated circuit device having resistance elements having reduced fluctuation of their resistance values and a fabrication method thereof are disclosed. More definitely, a protective film made of a gate electrode material of MISFETs formed on the main plane of a semiconductor substrate is disposed through an insulator film on the upper surface of the resistance elements comprising a semiconductor region which is formed by introducing an impurity of a first conductivity type into the main plane of the same semiconductor substrate.

Growing community of inventors

Takasaki, Japan

Kazunori Onozawa