Victor Company of Japan, Limited

Kazunori Nishikawa

Nobuaki Takahashi

Yoshiki Iwasaki

Makoto Komura

Isao Masuda

Hiroyuki Sugiyama

Shoji Ueno

Koji Tanaka

Kazuya Yamada

Takeshi Shibamoto

Yasuo Itoh

Shinji Nakamura

Yasuhisa Okabe

Masaaki Satoh

Katsuhiro Ohba

Hideaki Ozaki

Tatsuo Sawada

Nobuhide Ohsaki

Nobuaki Suda

Yasuhiro Yamada

Hideo Sato

Shunichi Shichijo

A digital signal has frames each composed of n data words and a parity code. One data word has m bits. The letters n and m represent natural numbers equal to or greater than 2. One frame of data words is written into a memory. When writing of one frame of the data words into the memory is completed, a write end flag is generated and written in the memory. After the detection of the write end flag, the data words are read out from the memory. An error is detected from the read data words and is corrected.

Method and apparatus for error correction

Parity is generated in accordance with digital data. The parity is added to the digital data to produce a coded signal. The coded signal is recorded. The recorded signal is reproduced. The reproduced signal is decoded and code word errors are corrected to reproduce the digital data. The number of symbols of the digital data equals m-(2n+1). The number of symbols of the parity equals 2n+1. Each of the symbols has l bits. The characters m and n denote natural numbers. The character l denotes a natural number equal to or greater than 2. Coding and decoding are performed by use of new-type Reed-Solomon code.

Digital data processing system

A first digital sound data of N-bits delivered from the input terminal is controlled by a mute control signal indicating either on-mute state signifying the state where mute operation is conducted or off-mute state signifying the state where no mute operation is conducted. This circuit includes a level control circuit, a register, a bit shift circuit, and a data selector. The level control circuit outputs a second digital sound data corresponding to the soundless state at the time of on-mute. It outputs data of which level gradually rises from the level of the soundless state to the level indicated by the first digital sound data at the beginning of off-mute and outputs the first digital duration at times subsequent thereto. Thus, for a duration at the beginning of off-mute, sound volume gradually rises. The register and the bit shift circuit gradually attenuate the first digital sound data to the level of the soundless state. Thus, for a duration at the beginning of on-mute, sound volume gradually lowers. The data selector selects the lowering operation by the time the above-mentioned rising operation is conducted, thus permitting a normal mute operation.

Digital muting circuit

A digital data transmitting system comprises a first circuit for transmitting digital data related to an information signal data in terms of sectors each having k words with respect to each channel, where k is a natural number. The transmission of the digital data is performed within a predetermined transmission time period once or a plurality of times according to a tolerance of data error rate for an information content of the digital data. The information signal data are among digital data related to a plurality of channels of information signals which are subjected to a digital modulation, and the plurality of channels of information signals are made up of a combination at least including the information signal data among three kinds of information signals. The three kinds of information signals are a non-compressed audio signal, a video signal, and the information signal data other than the non-compressed audio signal and the video signal. The system also comprises a second circuit for adding a code and a synchronizing signal to the digital data which are obtained from the first circuit, and for transmitting the digital data having the first code and the first synchronizing signal added thereto. The first code is at least indicative of a number of times the digital data are repeatedly transmitted within the predetermined transmission time period.

Digital data transmitting system for transmitting digital data a number

A data producing device in a signal reproducing apparatus, comprises a shift register supplied with synchronizing signals and codes which are time-sequentially reproduced from a recording medium, synchronizing signal detectors supplied with the synchronizing signals from the shift register, data transfer circuits provided in parallel with respect to each other and in series with the synchronizing signal detectors, and a control circuit for controlling the data transfer circuits so that a data is selectively read out and produced from a desired data transfer circuit among the plurality of data transfer circuits. The reproduced synchronizing signals and codes are transferred to the shift register and are read out from the shift register in response to a clock pulse having a predetermined frequency. The number of the synchronizing signal detectors is equal to the number of kinds of the synchronizing signals, and the synchronizing signal detectors are provided in parallel with respect to each other. Each of the synchronizing signal detectors detect a specific synchronizing signal. A data in a predetermined code among the codes supplied to the data transfer circuits is transferred to the data transfer circuits, when a synchronizing signal for discriminating the predetermined code is detected in the synchronizing signal detectors and supplied to the data transfer circuits.

Data producing device in a signal reproducing apparatus

A rotary recording medium has information signals recorded on a spiral or concentric tracks formed thereon as variations in geometrical configuration. The tracks comprise a mixture of digital recorded tracks which are recorded with a first modulated signal and analog recorded tracks which are recorded with a second modulated signal. The first modulated signal is a digital signal which has been time-sequentially multiplexed in terms of blocks at a transmission frequency of 44.1 kHz or a frequency extremely close to 44.1 kHz and has then been subjected to a modulation, where each of the blocks are constituted by a synchronizing signal, error correcting codes, and an error detecting code, which are added to a plurality of channels of digital data which are digitally modulated information signals. The second modulated signal is an analog modulated analog information signal at least including a composite video signal. A number of blocks recorded in one track turn of the digital recorded tracks is approximately equal to a product of the transmission frequency and a duration of one revolution of the rotary recording medium.

Rotary recording medium having track turns recorded with digital signal

A rotary recording medium reproducing apparatus comprises a reproducing circuit for picking up and reproducing pre-recorded signals from a rotary recording medium on which digital recorded tracks and analog recorded tracks coexist, a first reproducing circuit for reproducing a composite video signal having a horizontal scanning frequency of a predetermined television system from signals which are reproduced from the analog recorded tracks, among reproduced signals from the reproducing circuit, a second reproducing circuit for demodulating and reproducing original information signals from signals which are reproduced from the digital recorded tracks, among the reproduced signals from the reproducing circuit, an oscillator circuit for generating a signal having a frequency which is a natural number multiple of the horizontal scanning frequency of the predetermined television system, a servo circuit for rotating a motor which rotates the rotary recording medium, in synchronism with the output signal of the oscillator circuit, and a master clock signal generating circuit for supplying to the second reproducing circuit a signal which is obtained by frequency-multiplying the output signal of the oscillator circuit, as a master clock signal.

Rotary recording medium reproducing apparatus for reproducing

A synchronizing signal detecting circuit is used in a digital signal transmitting system which transmits a digital signal in which signals are time-sequentially multiplexed in terms of blocks, where each of the blocks are made up of digital data which are information signals subjected to a digital modulation, a synchronizing signal having a fixed pattern, and an error checking code arranged at a location separated from a location of the synchronizing signal by a predetermined number of bits. The synchronizing signal detecting circuit comprises a counter which is reset when a synchronizing signal detection output which has been discriminated as being correct by use of the error checking code is continuously obtained for N times, where N is a natural number greater than or equal to two.

Synchronizing signal detecting circuit in a digital signal transmitting

A memory circuit write-in system comprises a first circuit for supplying a digital signal including a time base fluctuation component, where one frame of the digital signal is constituted by at least a synchronizing signal and information data and the digital signal has a first repetition frequency with a period of one frame of the digital signal, a memory circuit for writing therein and reading out therefrom the digital signal supplied from the first circuit, and a second circuit for applying a write-in control signal to the memory circuit. The write-in control signal includes no time base fluctuation component and has a second repetition frequency substantially equal to the first repetition frequency, and the memory circuit is controlled by the write-in control signal so that write-in of the digital signal is carried out with a write-in period in a range of two times within the one frame period.

Memory circuit write-in system

A digital information recording system comprises a randomized digital signal forming circuit for forming a randomized digital signal by carrying out modulo-2 addition of at least digital information signals of a plurality of channels in a digital signal and a random code sequence which is generated independently, a detector for successively detecting values of each of a predetermined number of words from each of the digital information signals of a plurality of channels in the randomized digital signal, in terms of one word, and generating a detection signal only when values of bits in the one word are all '1' or all '0', a timing circuit for generating a timing signal for every period corresponding to a transmission period of a least significant bit in one word from each of the digital information signals of a plurality of channels, a polarity inverting circuit for passing the randomized digital signal unchanged during a period in which the detection signal is not generated from the detector, and inverting the polarity of the least significant bit in one word from each of the digital information signals of a plurality of channels in the randomized digital signal when simultaneously applied with the detection signal and the timing signal, and a recording circuit for recording a digital signal obtained from the polarity inverting circuit.

Digital information signal recording system

In a circuit arrangement for a disk player of the type arranged to reproduce information prerecorded in the form of pits, a variable gain circuit for changing the frequency characteristic of the reproduced signal is provided. The level of the reproduced signal is detected at high and low frequencies so as to produce a control signal the voltage of which varies in accordance with the difference between the level of the high frequency signal component and the level of the low frequency component. The control signal is then applied to the variable gain circuit receiving the reproduced signal so that the frequency characteristic of the reproduced signal will be controlled. Thus, the level of the reproduced signal is boosted at its high frequency range.

Circuit arrangement for a disk player for reproducing information

An information signal recording system comprises a circuit for generating pilot signals for tracking control, a circuit for generating a rectangular waveform signal of a specific frequency existing in an artificial synchronizing signal duration in every specific period and having almost no frequency component equal to and in the vicinity of the frequencies of the pilot signals, a circuit for pulse code modulating or difference modulating an information signal, further digital modulating the information signal, and obtaining a digital information signal existing in a time interval other than the artificial synchronizing signal duration. The digital information signal is recorded along a main track on a recording medium and the pilot signals are recorded along pilot signal tracks contiguous to the main track.

Systems for recording both information and pilot signals directly on

An angle modulated wave demodulation system demodulates an input angle modulated wave by means of a phase locked loop system which comprises a phase comparator, which is operated responsive to an input angle modulated wave. A voltage controlled oscillator is supplied with a part of the output of the phase comparator which controls its oscillation frequency. The oscillator supplies its oscillation frequency to the phase comparator. The phase locked loop system has a lock frequency range which decreases its width when the level of the input angle modulated wave is below a predetermined level. The portion of this lock range in which the width of the lock range decreases is positively utilized. The voltage controlled oscillator oscillates at a frequency equal to the center frequency of the carrier of the input angle modulated wave, when the phase locked loop becomes unlocked.

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Machida, Japan

Kazunori Nishikawa