Other

Tokyo Denki University

Kazunori Miyahara

Youichi Enomoto

Shuichi Nagasawa

Hideo Suzuki

Noriharu Miyaho

Tatsunori Hashimoto

Haruhiro Hasegawa

The present invention reduces the delay time to extremely short by monitoring the output/distribution unit of the exchange node to specify the unused time slot as write destination of the data and performing priority control by the priority control signal contained in the data. The traffic congestion is resolved by performing write output to the specified time slot regardless of the communication speed of the transmission path of the data. Furthermore, the present invention aims to provide the exchange node and the exchange node control method that ensures communication quality by using the connection type as the communication method since the delay time in communication can be reduced. The exchange nodeaccording to the present invention includes an input buffer unit, an identification unit, a distribution unit, a multiplexing circuit, a time slot allocation circuit, and an output/distribution unit. More preferably, a frame compression circuit, a frame decompression circuitand a priority determination circuitare arranged.

Exchange node and exchange node control method

A decimation filter includes a first circuit block for respectively delaying by one clock an input signal synchronized with a clock signal and for producing a plurality of delayed signals, adders for adding or merging by confluence buffers the delayed signals to obtain total signals and for feeding the total signals to one signal line, and a second circuit block for counting pulses of the total signals. The filter provides an analog-to-digital converter which processes signals at a high speed and which is resistive against overflow.

Decimation filter and signal processing method using the same

A rapid single-flux-quantum RSFQ logic circuit includes a first circuit portion having a first end grounded and having in-series connected first and second Josephson junctions. A second circuit portion has a first end grounded and has in-series connected third and fourth Josephson junctions. A first inductance element connects a second end of the first circuit portion to a second end of the second circuit portion. A tap is provided in the first inductance element, an input current signal being supplied to the tap. A bias current source is connected to a first connection node between the first and second Josephson junctions. A second inductance element connects the first connection node to a second connection node between the third and fourth Josephson junctions. A superconducting quantum interference device has fifth and sixth Josephson junctions and is coupled to the second inductance element through a magnetic field.

Rapid single-flux-quantum logic circuit and rapid single-flux-quantum output conversion circuit

A superconducting circuit device of a voltage-type logic device is large in current driving capability and, accordingly, electric power consumption; however, the switching speed is not so fast, and a superconducting circuit device of a fluxoid-type logic device is small in current driving capability and, accordingly, the electric power consumption; however the switching speed is faster than that of the superconducting circuit device of the voltage-type logic device, wherein the superconducting circuit device of the voltage-type logic device and the superconducting circuit device of the fluxoid-type logic device are selectively used in a superconducting circuit such as a superconducting random access memory, a superconducting NOR circuit and a superconducting signal converting circuit so as to realize small electric power consumption and high-speed switching action.

Superconducting circuit having superconductive circuit device of voltage-type logic and superconductive circuit device of fluxoid-type logic device selectively used therein

Growing community of inventors

Tokyo, Japan

Kazunori Miyahara