Fujitsu Corporation

Kazunori Masuyama

Sudheer Miryala

Patrick N Conway

Jeremy J Farrell

Takeshi Shimizu

Terumasa Haneda

Yuichi Ogawa

Yukio Nishimura

Shigeyoshi Ohara

Hitoshi Oi

Toshio Ogawa

Toshiyuki Yoshida

Martin Sodos

Yasushi Umezawa

Hiroshi Ishizawa

Yuuji Hanaoka

Norio Kaido

Prabhunandan B Narasimharmurthy

Prabhu Murthy

Shunichi Ihara

Prabhunandan B Narasimhamurthy

Shigeyoshi O'Hara

In response to a request from a central processing unit (CPU)(i.e., firmware) of a node, a transfer control unitof a direct memory access (DMA) controllertransmits a message and data to another discretionary nodeby way of a serial bus, a switchor the like. In this event, the firmware stores data to be transmitted, a message, and a descriptor thereof in memory. In the case of requesting the transmission of the message, the descriptor contains a flag indicating 'whether or not there is a need to wait for a response from the data transmission destination'. If the flag is set to ON, the transfer control unitnotifies the firmware of a simulated completion immediately instead of waiting for a completion response from the transmission destination node

DMA controller, node, data transfer control method and storage medium

To be able to transmit a response packet to the original request node after a bus ID/a device ID is replaced in the PCI-Express switch for a PCI-Express communication system, a unique node ID for indicating each node is set to the nodes. Additionally, it is confirmed whether or not the packet is transferred in the correct order in a series of packet transfers. For that purpose, a sequence code indicating the sequence number of a packet in a series of packet transfer is set in an address field of a packet of data transfer.

PCI-express communications system

A file control system performing DMA (direct memory access) transfer is provided. The file control system includes file control devices, and each of the file control devices is provided between a host computer and an external storage device. A first file control device among the file control devices checks for errors in the data read from a memory, changes the error detection code added to the read data from a first error detection code to a second error detection code, changes at least a part of the data when an error is detected, and executes DMA-transfer of the data, which is changed or is not changed, to a second file control device of the transfer destination.

File control system and file control device

A computer system enable system operation by hiding the peculiarity of an upstream port of a switch in a computer system in which a plurality of CPU units are interconnected by a PCI Express switch. When a CPU unit, which is connected to the upstream port of a serial connect switch interconnecting the plurality of CPU units, is unable to operate, and the links between the CPU units and the switch cannot be established, a management controller in the switch unit is selected as a device of the upstream port.

Computer system using serial connect bus, and method for interconnecting a plurality of CPU using serial connect bus

Before the link of each port of a switch provide with a plurality of ports for interconnecting a plurality of process nodes by a serial bus is established, it is checked whether each process node is mounted. Then, of the plurality of ports, a port to which one of mounted process nodes is connected is assigned as an upstream port and the other ports are assigned as downstream ports.

Apparatus for interconnecting a plurality of process nodes by serial bus

A storage system has a plurality of control modules for controlling a storage device for accesses from a mainframe host and an open system host respectively supporting different protocols. An open channel adaptor and a mainframe channel adaptor are separately provided. The mainframe channel adaptor is connected to a plurality of control managers via front routers and performs parallel write access from the mainframe host for mirroring. In the write processing for the mainframe host, the connection is maintained until the completion of processing. In particular, even in case of a write miss, disk read processing can be performed in parallel, thus contributing to the high-speed processing in case of the write miss. Further, for an access from the open system host, a high throughput can be obtained.

Data storage system and control apparatus with a switch unit connected to a plurality of first channel adapter and modules wherein mirroring is performed

A system and method for fault containment and error handling within a domain in a partitioned computer system includes a system manager having read and write access to a resource definition table. The system manager is adapted to quiesce the system when failure occurs within a domain, identify an allocated resource associated with the failed domain, identify a non-failed domain, and exit the quiesce mode for the non-failed domain, thereby containing a failure within the failed domain. The system manager further handles an error within the failed domain by deallocating a resource allocated to the failed domain so that the resource becomes available to non-failed domains.

Fault containment and error handling in a partitioned system with shared resources

A method and system enables dynamic support of memory mapping devices in a multi-node computer system. One of central process unit (CPU) nodes determines a total amount of MMIO address spaces that are needed for all MMIO devices and generates an optimized granularity to support the total amount of MMIO address spaces. Based on the granularity, a CPU node controller configures MMIO range registers of the interconnect and other MMIO registers in IO nodes and CPU node controllers to support dynamic changes of MMIO address space requirements of the system.

Dynamic determination of memory mapped input output range granularity for multi-node computer system

A system and method for passing messages between domains with low overhead in a multi-node computer system. A CPU node in a sending domain issues a request to a memory node in a receiving domain using memory-mapped input/output window. This causes the message to be transmitted to a coherent space of the receiving domain. All messages are cache-line in size. A small portion of each cache line, cyclic counter field, is overwritten before the cache line is written in the coherent address space of the receiving domain. A massaging driver polls the cyclic count field of the cache line in the processor cache to determine when the next message is written in the coherent address space of the receiving domain. This allows the CPU to detect when the last received message is written into the coherent address space of the receiving domain without generating transactions on CPU interface.

System and method for low overhead message passing between domains in a partitioned server

A mechanism for balancing message traffic in a multi-chassis fully interconnected computer system partitioned into multiple domains allows the system to identify I/O transactions, to route I/O transactions over inter-domain cables, and to route non-I/O transactions over intra-domain cables. This beneficially reduces message traffic congestion on intra-domain cables.

Routing mechanism for static load balancing in a partitioned computer system with a fully connected network

A method and system transfers data between intra-node firmware and inter-nodes firmware in a multi-node computer system using reduced hardware resources. A set of control codes and data transfer functions are provided to enable data communications between computer nodes and inter-nodes controller through a one-byte control module and a one-byte data module.

Data transfer in multi-node computer system

A domain partitioning system for a multi-node computer system is disclosed. An external server manager is coupled to a domain configuration unit by a dedicated sideband channel. The server manager has write privileges to the domain configuration unit that allows the server manager to control the domain partitioning and the routing tables. None of the domains of the computer system are permitted write access to the domain configuration unit. In one embodiment, the domain configuration unit is a set of domain partition registers and routing table registers coupled to a system interconnect.

System and method for partitioning a computer system into domains

In a distributed multi-node computer system each switch provides routing of data packets between CPU nodes, I/O nodes, and memory nodes. Each switch is connected through a corresponding I/O node to a network interface controller (NIC) for transferring data packets on a network. Each NIC is memory-mapped. Part of the system address space forms a send window for each NIC connected to a corresponding switch. A mechanism for controlling data packets transmission is defined such that each CPU write to a NIC send window is atomic and self-defining, i.e., it does not rely on immediately preceding write to determine where the data packet should be sent. Using 'address aliasing', CPU writes to the aliased part of the NIC send window are always directed to the NIC connected to the same switch as the CPU which did the write.

Mechanism to improve performance in a multi-node computer system

A system and method of logically partitioning shared memory structures between computer domains is disclosed. In one embodiment, each domain is assigned a unique address space identifier. The unique address space identifier preferably has tag extension and index extension bits. This permits the tag and index bits of a conventional local domain address to be extended with tag extension and index extension bits. Data entries in the shared memory structure may be accessed using an extended index value. Hits may be determined using an extended tag value.

Method and system for logical partitioning of cache memory structures in a partitoned computer system

A multi-node computer system includes a plurality of I/O nodes, CPU nodes, memory nodes, and hybrid nodes connected via an interconnect. A CPU node or an I/O node issues a request. An address decoder residing in the interconnect decodes the request to determine whether the request is a coherent memory request. The address decoder also determines a physical destination node address of the request based on a logical node address stored in the request.

Growing community of inventors

Kanazawa, Japan

Kazunori Masuyama