Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kazunori Masuda

Hiroshi Watanabe

Koichi Fukuda

Masato Endo

Kiyomi Naruke

Tsutomu Takahashi

Hiroyuki Kutsukake

Norihisa Arai

Yoshiko Kato

Yoshihisa Watanabe

Kazuo Hatakeyama

Masanori Hatakeyama

Takuya Kusaka

Yukio Nishida

Yuuichi Tatsumi

Masato Sugawara

Naoyuki Kondo

Naoya Kami

Masatoshi Watarai

According to one embodiment, the insulating layer is provided on the terrace portions. The plurality of contact portions extend through the insulating layer in the stacking direction and contact the terrace portions. The second columnar portion extends through the insulating layer and through the second stacked portion in the stacking direction, and includes a second semiconductor body contacting the first semiconductor region. The first insulating portion divides the first semiconductor region in the first direction. The first insulating portion is provided under a boundary portion between the first stacked portion and the second stacked portion.

Semiconductor device

A semiconductor device according to an embodiment, includes a plurality of wires, a first dielectric film, and a second dielectric film. The plurality of wires are arranged above a semiconductor substrate so as to extend in a first direction and aligned via a first cavity. The first dielectric film has a plurality of portions arranged above the plurality of wires so as to extend in a second direction substantially perpendicular to the plurality of wires and aligned along the first direction via a second cavity leading to the first cavity. The second dielectric film is formed above the first dielectric film so as to cover the second cavity.

Semiconductor device and method for fabricating semiconductor device

According to one embodiment, a semiconductor device includes: a semiconductor layer of a first conductivity type, and the semiconductor layer having a first and a second surfaces; a first conductive layer penetrating from the first surface side to the second surface side of the semiconductor layer; a first semiconductor region of a first conductivity type surrounding part of the first conductive layer on the second surface side of the semiconductor layer, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor layer; and a first insulating film provided between the first conductive layer and the semiconductor layer and between the first conductive layer and the first semiconductor region, a concentration of an impurity element contained in the first semiconductor region being higher than a concentration of an impurity element contained in the semiconductor layer.

According to one embodiment, a semiconductor device includes at least one semiconductor region provided in a semiconductor substrate, and a capacitor group including a plurality of capacitors provided in the semiconductor region, each capacitor including a capacitor insulating film provided on the semiconductor region, a capacitor electrode provided on the capacitor insulating film, and at least one diffusion layer provided in the semiconductor region adjacent to the capacitor electrode.

This semiconductor device comprises a semiconductor substrate, a gate insulating film formed thereon, and a gate electrode formed through the gate insulating film on the semiconductor substrate. The first silicon nitride film is formed on the upper surface of the gate electrode, and a protection insulating film is formed on the side thereof. The second silicon nitride film is formed on the side of the protection insulating film. The third silicon nitride film is formed on the upper surface of the protection insulating film, and the bottom thereof is formed on a higher position than the bottom of the first silicon nitride film.

Semiconductor device and method of manufacturing the same

Disclosed is a semiconductor device comprising a first transistor and a second transistor formed on a semiconductor substrate, wherein a gate side wall of the second transistor has a thickness equal to that of a gate side wall of the first transistor, wherein each of the first and second transistors has an inner low impurity diffusion region and an outer high impurity diffusion region, and wherein the size of the inner low impurity diffusion region of the second transistor along the surface of the semiconductor substrate is larger than that of the inner low impurity diffusion region of the first transistor.

Disclosed is a contact structure between the bit line and the source/drain region in an EEPROM. An element region is isolated by a trench type element isolation region in a silicon substrate. The source/drain region is formed in the portion of the element region, that is surrounded by the trench type element isolation region and a multilayered gate. A silicon nitride film covers the surface of the trench type element isolation region and that of the multilayered gate, and an interlevel insulating film made from silicon dioxide is formed. A contact hole is formed in the interlevel insulating film. The source/drain region and the silicon nitride film are exposed in the contact hole. A bit line is connected to the source/drain region through the contact hole.

Growing community of inventors

Yokohama, Japan

Kazunori Masuda