Fujitsu Corporation

Fujistu Limited

Kazunori Kasuga

Hirofumi Shimizu

Katsutoshi Kondo

Yoshinori Mesaki

Masaki Tosaka

Osamu Ishibashi

Noriyuki Matsui

Yuzo Usui

Masao Matsuda

A regulator device includes: a plurality of regulators that are equipped in parallel between a power input terminal and a power output terminal and converts a power inputted from the power input terminal to output to the power output terminal; a dummy load circuit that is coupled to a power output system different from a power output system to the respective power output terminal of the plurality of regulators; a selector that selects a regulator to carry out an output to the power output terminal and a regulator to carry out an output to the dummy load circuit among the plurality of regulators; and a controller that obtains conversion efficiency characteristic information representing a characteristic of power conversion efficiency relative to a current flowing in the dummy load circuit for the regulator to carry out an output to the dummy load circuit.

Regulator device

A regulator device includes: a power input terminal; a power output terminal; a plurality of regulators each including an operating FET and a monitoring FET to be driven together with the operating FET, the plurality of regulators being arranged in parallel between the power input terminal and the power output terminal; and a controller configured to drive the operating FET and the monitoring FET included in one of the regulators, when the controller determines whether the monitoring FET included in the one of the regulators have degraded, the controller configured to stop driving the operating FET and the monitoring FET included in the one of the regulators and configured to drive the operating FET and the monitoring FET included in another of the regulators.

Regulator device having degradation detection

A regulator apparatus having an input terminal and an output terminal, the regulator apparatus includes: a plurality of regulators arranged in parallel between the input terminal and the output terminal; an conversion efficiency characteristic information obtaining unit that obtains conversion efficiency characteristic information representing a characteristic of a conversion efficiency with respect to an output current with regard to each of the plurality of regulators; a memory that stores the conversion efficiency characteristic information of each of the plurality of regulators obtained by the conversion efficiency characteristic information obtaining unit; and a switching control unit that performs a switching control on the plurality of regulators based on a value of the output current output from the output terminal and the conversion efficiency characteristic information stored in the memory.

Optimized conversion efficiency for regulator apparatus with plural parallel regulators

An information processing device includes a first storage sectionthat includes a plurality of cells to store data; a second storage sectionthat holds refresh intervals and the states of implementation of refresh operations for each of a plurality of the cells; and a control section that controls the refresh operation of each of the cells on the basis of the refresh intervals and the states of implementation of refresh operations held by the second storage section. The information processing device controls the refresh operation of each of the cells at refresh intervals set for respective cells.

Information processing device including a plurality of cells to store data, storage control device that controls a storage section including a plurality of cells to store data, and storage control method of controlling a refresh operation of a storage section including a plurality of cells to store data

A nonvolatile memory includes a memory cell array including a plurality of memory cells, each of the memory cells capable of storing electric charges nonvolatilly, a first sense amplifier for comparing a voltage produced by one of the selected memory cells to be read out with a first threshold value for distinguishing between a write state and an erase state of the selected memory cell, a second sense amplifier for comparing the voltage produced by one of the selected memory cell with a second threshold value having a greater voltage than the first threshold voltage, and a write unit for rewriting data of the selected memory cell when the first and the second sense amplifiers produce different sense outputs from each other.

Nonvolatile memory

A nonvolatile semiconductor storage device includes a plurality of cells for storing data on a basis of charges stored nonvolatilly, a write unit for writing and erasing data on the cell by injecting or extracting charges into or from the cell, a comparator for comparing the voltage produced by a selected cell to be read out with a threshold, a read unit for outputting read data on the basis of the comparison result by the comparator, and a threshold update unit for updating the threshold of the comparator according to the voltage produced by the selected cell.

Nonvolatile semiconductor storage device, controller and threshold adjustment method

An information processing system includes a dynamic random access memory, a processor for information processing in cooperation with the dynamic access memory, and a built-in diagnosis module including a longevity evaluation device, the longevity evaluation device comprising, a timer for measuring an elapsed time after data is entered into a memory device, a read controller for reading the data from the memory device when the elapsed time reaches a predetermined time, and an evaluator for evaluating a longevity of the memory device based on an existence of an error in the data read by the read controller and the elapsed time.

Information processing system

A semiconductor storage apparatus comprising: a plurality of cells that store data; a threshold determination section that determines, based on management information that is used to manage data, a binary or multiple-valued form by which values are written to a plurality of the individual cells and determines a threshold based on the determined form of values that are to be written to a plurality of the individual cells; and a write section that writes the data to a plurality of the cells on the basis of the threshold determined by the threshold determination section.

Semiconductor storage apparatus, control apparatus and control method

A disk apparatus has a memory storing boot-information; and a stop section which reads, upon receipt of a stop event, the boot-information from a disk and checks the read information against the boot-information in the memory. This section updates contents of the memory to store therein the same boot-information as that in the disk and writes flag-information indicating that the same boot-information is stored in the memory when a difference is found by the checking. The apparatus also has a start section which judges, upon receipt of a start event, whether or not the flag-information is stored in the memory, reads the boot-information from the memory and activates a device used with the apparatus while deleting the flag-information when the flag-information is stored. This section reads the boot-information from the disk to activate the device and writes the read boot-information in the memory when the flag-information is not stored.

Disk apparatus and electronic apparatus

A load detection circuitdetects a load value of a load portionvia a terminal DQ. A reference load, corresponding to the load of a probe, is output from a reference load output section. A comparison circuitjudges whether the detected load value matches the reference load, and outputs a control signal if matched. If this control signal is input, an input and output bufferstops the output of the data from a memory cellto the terminal DQ, or outputs a specific logic.

Semiconductor device and control method in semiconductor device

A memory drive circuit includes at least one memory module constructed of a plurality of memory elements, a memory controller for driving said memory module, and a buffer, disposed between the memory module and the memory controller, for receiving a drive signal from the memory controller and transmitting the received drive signal to the memory module. Signal reflection noises produced in the memory module are absorbed by the buffer.

Growing community of inventors

Kawasaki, Japan

Kazunori Kasuga