Texas Instruments Corporation

Kazunori Hayata

Masood Murtuza

Matthew David Romig

Siva Prakash Gurrum

Darvin R Edwards

Kengo Aoya

Dan Okamoto

Yohei Koto

Shohta Ujiie

A packaged integrated circuit (IC) includes a substrate including a first substrate pad disposed on a first side of the substrate, an IC die disposed on the first side of the substrate, and a first insulating layer molded over the IC die and the substrate. The IC die includes a first die pad on a side of the die opposite from a side of the die adjacent to the first side of the substrate. The first insulating layer includes a first channel extending through the first insulating layer to the first substrate pad, a second channel extending through the first insulating layer to the first die pad, conductive paste filling the first channel and in contact with the first substrate pad, and conductive paste filling the second channel and in contact with the die pad.

Circuit substrate interconnect

A method of assembling semiconductor devices includes applying a metal paste including a plurality of metal particles having an average size less than 50 nanometers and a binder material onto a metal terminal of a package substrate. The metal paste is processed including a heat up step in a reducing gas atmosphere and then a vacuum sintering step at a temperature of at least 200&#xb0; C. for forming a sintered metal coating. A semiconductor die is attached onto a die attach area of the package substrate. A bond wire is then connected between a bond pad on the semiconductor die and the sintered metal coating on the metal terminal.

Multi-step sintering of metal paste for semiconductor device wire bonding

In fabricating a semiconductor device first layers are formed of sintered bondable and solderable metal on a carrier strip. The first layers are patterned into first pads and second pads. A set of first pads is surrounding each second pad. The first pads are spaced from the second pad by gaps. The patterned layers are formed of agglomerate metal vertically on the first layers of sintered bondable and solderable metal of the first pads and of the second pad. The second layers are formed of sintered bondable and solderable metal vertically on the layers of agglomerate metal of the first pads.

Method for contacting agglomerate terminals of semiconductor packages

A plastic package () in which a semiconductor chip () is adhesively () attached to a metal stripe () having an agglomerate structure, and electrically connected to bondable and solderable metal stripes () having particulate structures; metal stripes () are touching metal stripes () of agglomerate structure to form vertical stacks (); coats of solder () are welded to the agglomerate metal stripes (and).

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Beppu-Oita, Japan

Kazunori Hayata