Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Ulsi Engineering Corp.

Hitachi Tohbu Semiconductor, Ltd.

Hitachi Vlsi Engineering Corp.

Renesas Technologies Corporation

Hitachi, Ltd. & Engineering Corp.

Hitachi Vlsi

Hitachi Vsli Eng. Corp.

Kazunori Furusawa

Masachika Masuda

Hirotaka Nishizawa

Tamaki Wada

Kenji Osawa

Junichiro Osako

Haruji Ishihara

Kazuo Yoshizaki

Satoshi Hatakeyama

Kunihiro Katayama

Kenichi Kaki

Jun Kitahara

Motoki Kanamori

Atsushi Shikata

Tsunehiro Tobita

Yosuke Yukawa

Kenji Kozakai

Yuusuke Jono

Masaaki Terasawa

Takeshi Furuno

Masashi Wada

Masahito Takahashi

Michiko Odagiri

Tomoyuki Ishii

Hideaki Kurata

Yoshiaki Kamigaki

Yoshihiro Ikeda

Hidefumi Mukohda

Yasunori Ikeda

Toshihiro Tanaka

Shoji Shukuri

Hitoshi Kume

Takayuki Tamura

Toshio Sasaki

Masataka Kato

Nagamasa Mizushima

Hiroaki Kotani

Yoshifumi Kawamoto

Shinichi Minami

Tomihisa Hatano

Shinji Nabetani

Yoshikazu Nagai

Flash memory is rapidly decreasing in price. There is a demand for a new memory system that permits size reduction and suits multiple-value memory. A flash memory of AND type suitable for multiple-value memory with multiple-level threshold values can be made small in area if the inversion layer is utilized as the wiring; however, it suffers the disadvantage of greatly varying in writing characteristics from cell to cell. Another promising method of realizing multiple-value memory is to change the storage locations. This method, however, poses a problem with disturbance at the time of operation. The present invention provides one way to realize a semiconductor memory device with reduced cell-to-cell variation in writing characteristics. The semiconductor memory has a source region and a drain region, which are formed parallel to each other, and an assist electrode which is between and parallel to the source and drain regions without overlapping, so that it uses, at the time of writing, the assist electrode as the assist electrode for hot electrons to be injected at the source side and it uses, at the time of reading, the inversion layer formed under the assist electrode as the source region or the drain region.

Semiconductor memory device

A memory card () includes an electrically rewritable non-volatile memory (), a data processor () having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit () having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory () for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.

Nonvolatile semiconductor memory apparatus having buffer memory for storing a program and buffering work data

On an adapter mounting portionhaving a projecting cross section which is formed on a capof a small-sized memory card, a recessed portion of an adapterside is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the small-sized memory cardcan maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory cardcan be used also in equipment which is designed to cope with the existing memory cards.

Memory card with connecting portions for connection to an adapter

Memory card having buffer memory for storing testing instruction

Memory card with a cap having indented portions

Memory card with an adaptor

On an adapter mounting portionhaving a projecting cross section which is formed on a capof a small-sized memory card, a recessed portion of an adapterside is fitted so that both parts are formed as an integral unit in a replaceable manner Accordingly, the small-sized memory cardcan maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory cardcan be used also in equipment which is designed to cope with the existing memory cards.

Memory card

To realize a semiconductor memory device with reduced cell-to-cell variation in writing characteristics a semiconductor memory has a source region and a drain region, which are formed parallel to each other, and an assist electrode which is between and parallel to the source and drain regions without overlapping, so that at the time of writing, the assist electrode is used as an assist electrode for hot electrons to be injected at the source side and at the time of reading, an inversion layer formed under the assist electrode is used as the source region or the drain region.

Memory card having a buffer memory for storing testing instruction

A flash memory based file memory device built in an information processing apparatus enables fast file access. The file memory device is provided with a parallel arrangement of memory element groups having a unit erasure block size greater than the data bus width of the memory device and a data access width smaller than the data bus, a file division unit for dividing file data that consists of one or more unit storage data blocks into combined blocks that consists of a combination of arbitrary unit storage data blocks, a data distribution unit for combining arbitrarily data on the data bus in terms of the unit data size equal to the data access width and making the combined data correspondent to an arbitrary combination of memory element groups equal in number to the unit size data, and a control unit for controlling the data distribution unit such that each combined block is stored in the file memory device by being correspondent to one of the arbitrary combinations of memory element groups.

File memory device and information processing apparatus using the same

On an adapter mounting portionhaving a projecting cross section which is formed on a capof a small-sized memory carda recessed portion of an adapterside is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the small-sized memory cardcan maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory cardcan be used also in equipment which is designed to cope with the existing memory cards.

Semiconductor device and a method of manufacturing the same

A semiconductor file memory device, and an information processing system incorporating the device, uses flash memories to achieve fast file access performance. The file memory device includes a parallel arrangement of memory element groups having a unit erasure block size greater than the data bus width of the memory device, and a data access width smaller than the data bus; a file division unit for dividing file data having one or more unit storage data blocks into combined blocks that include a combination of arbitrary unit storage data blocks; a data distribution unit for arbitrarily combining data on the data bus having a unit data size equal to the data access width, and for making the combined data correspond to an arbitrary combination of memory element groups equal in number to the unit size data; and a control unit for controlling the data distribution unit so that each combined block is stored in the file memory device based on a correspondence between the combined block and arbitrary combinations of memory elements.

A memory card ( ) includes an electrically rewritable non-volatile memory ( ), a data processor ( ) having a function of executing instructions and managing the allocation of file data in the non-volatile memory, an interface control circuit ( ) having a function of establishing an external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory ( ) for temporarily storing the file data. The interface control circuit includes command control means for decoding a first command externally supplied and for instructing the data processor to fetch an instruction from the buffer memory and to operate.

In the present invention, disclosed is a semiconductor memory device capable of reducing the number of erasing times of each block allocated to a cluster or the number of blocks to be erased in one writing to the minimum. As an embodiment of the present invention, when a host system performs accessing, for each cluster as a unit, to the FAT partition prepared on a flash memory of the semiconductor memory device , a CPU adds an address offset value held by address offset storage section to a logical address specified by the host system , whereby a logical address of a head sector of the cluster correspond to a physical address of a head sector of a unit block for erasing/writing data in the flash memory

Semiconductor memory device with block alignment function

Growing community of inventors

Kodaira, Japan

Kazunori Furusawa