Sanyo Electric Co., Ltd.

Kazunori Chida

Yutaka Shimizu

In a liquid crystal television, a display controller prevents burning of a liquid crystal panel due to irregularity in a synchronization signal. A counter of a liquid crystal display controller detects a period of a horizontal synchronization signal and a vertical synchronization signal. A comparator compares a count value with a predetermined minimum value Min and maximum value Max. When the count value is out of a range, a synchronization pulse generator generates a synchronization pulse at a time when the period falls within a predetermined range. A selector outputs an input synchronization signal when the period is within the range and outputs the synchronization pulse obtained from the synchronization pulse generator when the period is out of the range.

Liquid crystal display controller

Disclosed is a video signal processing apparatus comprising a plurality of line memories to which in sequence input video signal data is written on a line-by-line basis; a timing controller for controlling a timing to write video signal data to the plurality of line memories and a timing to read video signal data from the plurality of line memories; a computation output portion for computing video signal data read from the plurality of line memories and outputting video signal data differing in resolution which is determined by a pixel count in the horizontal direction and a line count in the vertical direction; and a line controller which vary the pixel count in specified lines of video signal data obtained from the computation output portion, depending on a conversion rate of the video signal data resolution.

Video signal processing apparatus and integrated circuit

An input video signal is reduced according to size reduction ratio data K in an input processing section and written into alternate field memories. The written reduced video signal is alternately read from the field memories in a display processing section and processed for window displaying. Video reduction control sections are provided on the respective input and display sides, so that various signals, such as RHOLD, ADCANS, RACK signals, etc., are exchanged therebetween. When a size reduction ratio data K is changed, on the display side a read memory is fixed on a first field memory and size data is fixed, while on the write side video data is written into a second field memory, based on the new reduction ratio. After updating the size data on the display side, video data is read from the second field memory at the new reduction ratio. When reading and writing operations with respect to the second field memory are finished, fixing of the respective memories is released, whereby a signal processing operation returns to a normal operation.

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Ota, Japan

Kazunori Chida